aopen/dxplplusu: Replace use of dev_find_slot()

To use fixed PCI bus numbers is always invalid.

Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

2 files changed, 26 insertions, 56 deletions

diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c
index 039e4ecc6a..cc6835b939 100644
--- a/src/mainboard/aopen/dxplplusu/acpi_tables.c
+++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c
@@ -20,13 +20,17 @@
 
 #include <arch/acpi.h>
 #include <device/pci.h>
-#include <assert.h>
-#include "bus.h"
+
+#define IOAPIC_ICH4		2
+#define IOAPIC_P64H2_BUS_B	3	/* IOAPIC 3 at 02:1c.0 */
+#define IOAPIC_P64H2_BUS_A	4	/* IOAPIC 4 at 02:1e.0 */
+
+#define INTEL_IOAPIC_NUM_INTERRUPTS	24	/* Both ICH-4 and P64-H2 */
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
 	unsigned int irq_start = 0;
-	struct device *dev = NULL;
+	struct device *bdev, *dev = NULL;
 	struct resource* res = NULL;
 
 	/* SJM: Hard-code CPU LAPIC entries for now */
@@ -36,25 +40,30 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
 
 	/* Southbridge IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4,
+					   0xfec00000, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
+	bdev = pcidev_on_root(2, 0);
 	/* P64H2 Bus B IOAPIC */
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
-	if (!dev)
-		BUG();		/* Config.lb error? */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+	if (bdev)
+		dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
+						   IOAPIC_P64H2_BUS_B, res->base, irq_start);
+		irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+	}
 
 	/* P64H2 Bus A IOAPIC */
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
-	if (!dev)
-		BUG();		/* Config.lb error? */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
+	if (bdev)
+		dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
+						   IOAPIC_P64H2_BUS_A, res->base, irq_start);
+		irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+	}
 
 	/* Map ISA IRQ 0 to IRQ 2 */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h
deleted file mode 100644
index 12eef12381..0000000000
--- a/src/mainboard/aopen/dxplplusu/bus.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef DXPLPLUSU_BUS_H_INCLUDED
-#define DXPLPLUSU_BUS_H_INCLUDED
-
-/* These were determined by seeing how coreboot enumerates the various
- * PCI (and PCI-like) buses on the board.
- */
-
-#define PCI_BUS_ROOT		0
-#define PCI_BUS_AGP		1	/* AGP */
-#define PCI_BUS_E7501_HI_B	2	/* P64H2#1 */
-#define PCI_BUS_P64H2_B		3	/* P64H2#1 bus B */
-#define PCI_BUS_P64H2_A		4	/* P64H2#1 bus A */
-#define PCI_BUS_ICH4		5	/* ICH4 */
-
-/* IOAPIC addresses determined by coreboot enumeration. */
-/* Someday add functions to get APIC IDs and versions from the chips themselves. */
-
-#define IOAPIC_ICH4		2
-#define IOAPIC_P64H2_BUS_B	3	/* IOAPIC 3 at 02:1c.0  MBAR = fe300000 DataAddr = fe300010 */
-#define IOAPIC_P64H2_BUS_A	4	/* IOAPIC 4 at 02:1e.0  MBAR = fe301000 DataAddr = fe301010 */
-
-#define INTEL_IOAPIC_NUM_INTERRUPTS	24	/* Both ICH-4 and P64-H2 */
-
-#endif