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authorAngel Pons <th3fanbus@gmail.com>2020-06-15 23:56:28 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-09 18:14:02 +0000
commit649505b077ca11d03a176fc8da392498ff7f1d52 (patch)
treebc1e7643b2b5b02e74f205cbeccc30ef1fb524f3
parent822b267a8cfd8127f4b2a35942c01589a604ee5f (diff)
downloadcoreboot-649505b077ca11d03a176fc8da392498ff7f1d52.tar.xz
mb/asrock/b85m_pro4: Add Super I/O GPIO table
Information taken from the boardviews. We are not configuring any GPIO in bootblock, but we may want to do so in the future. Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/asrock/b85m_pro4/bootblock.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c
index 9b3746c521..0cedcd6e47 100644
--- a/src/mainboard/asrock/b85m_pro4/bootblock.c
+++ b/src/mainboard/asrock/b85m_pro4/bootblock.c
@@ -9,6 +9,41 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
+/*
+ * Asrock B85M Pro4 Super I/O GPIOs
+ *
+ * +------+-----+---------------------------+
+ * | GPIO | Pin | Description |
+ * +------+-----+---------------------------+
+ * | GP00 | 2 | N/C |
+ * | GP01 | 4 | CPU Fan 4-pin tach enable |
+ * | GP02 | 5 | CPU Fan 3-pin tach enable |
+ * | GP03 | 8 | CPU Fan 3-pin FON# signal |
+ * | GP04 | 9 | N/C |
+ * | GP05 | 11 | N/C (+1.05V_PCH_GPIO) |
+ * | GP06 | 12 | N/C (+1.5V_PCH_GPIO) |
+ * | GP07 | 13 | N/C |
+ * +------+-----+---------------------------+
+ * | GP10 | 123 | N/C (VCCM_OV1) |
+ * | GP11 | 122 | N/C (VCCM_OV2) |
+ * | GP12 | 121 | N/C (VCCM_OV3) |
+ * | GP13 | 120 | N/C (VCCM_STEP) |
+ * | GP14 | 119 | Assert HDA_SDO (SIO_GP14) |
+ * | GP15 | 118 | N/C (PWM_THROTTLE) |
+ * | GP16 | 117 | OTP for VCORE (OTE_GATE1) |
+ * | GP17 | 116 | N/C (IMON_GPIO) |
+ * +------+-----+---------------------------+
+ * | GP70 | 93 | PWR_FANIN |
+ * | GP71 | 92 | N/C |
+ * | GP72 | 91 | N/C (SIO_PIN91) |
+ * | GP73 | 90 | CHA2_FANIN |
+ * | GP74 | 89 | N/C (SIO_PIN89) |
+ * | GP75 | 88 | N/C (SIO_PIN88) |
+ * | GP76 | 87 | HDA reset gate (GP76) |
+ * | GP77 | 86 | HDD_LED gate |
+ * +------+-----+---------------------------+
+ */
+
void mainboard_config_superio(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);