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authorAngel Pons <th3fanbus@gmail.com>2020-09-15 00:51:36 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-17 19:59:59 +0000
commit6549661b9cc94add8c203a26f5f29af255668e4e (patch)
tree2fc190924e866f6c7ee01ba24acd2bc53086d273
parentd25e2f6c80fbeca955fe698ad6822e4bf598ebd2 (diff)
downloadcoreboot-6549661b9cc94add8c203a26f5f29af255668e4e.tar.xz
nb/intel/pineview: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I347466f56d3d5fb3793b3a25e4a825c844e50d42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/northbridge/intel/pineview/pineview.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 19b9584f3f..03fa318a14 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -59,17 +59,17 @@
* EPBAR - Egress Port Root Complex Register Block
*/
-#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
-#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
-#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x)))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
/*
* DMIBAR
*/
-#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
-#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
-#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x)))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
enum fsb_clk {
FSB_CLOCK_667MHz = 0,