diff options
| author | Boris Mittelberg <bmbm@google.com> | 2021-03-25 22:34:28 +0000 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-04-02 16:10:27 +0000 |
| commit | 6c2f80c4a2ea39679c80368387d8a20854a985b2 (patch) | |
| tree | 2848a7998267f40944d9944dfa6b4ce40ded0ecd | |
| parent | 65fce098e3d4ba7b884bee040885acf8b44d05c2 (diff) | |
| download | coreboot-6c2f80c4a2ea39679c80368387d8a20854a985b2.tar.xz | |
mainboard/google/brya: Enable tight timestamp
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device
BUG=none
TEST=manual test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h index fba653bd75..a4b8829af4 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -64,4 +64,6 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ + #endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 578fac9de9..0de7ffd36c 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -16,5 +16,7 @@ #define GPIO_EC_IN_RW GPP_F18 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_F9 +/* GPIO IRQ for tight timestamps / wake support */ +#define EC_SYNC_IRQ GPP_F17_IRQ #endif /* __BASEBOARD_GPIO_H__ */ |