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authorMarshall Dawson <marshalldawson3rd@gmail.com>2020-06-18 10:36:40 -0600
committerFelix Held <felix-coreboot@felixheld.de>2020-06-22 22:57:13 +0000
commit6e5e24e2b307ec18a0eb36f2141349dcf0304907 (patch)
treedd4f6ba288f67d4e9f09d3babd47958a15accf00
parent03743b7fa3217f13f019bce9b8680c5936375d71 (diff)
downloadcoreboot-6e5e24e2b307ec18a0eb36f2141349dcf0304907.tar.xz
cbmem: Remove IDs for TSEG and BERT
Remove the changes added in commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data" No platform uses either ID. TSEG in cbmem is incompatible with stage cache. BERT reserved data in cbmem is unusable in Linux. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/commonlib/include/commonlib/cbmem_id.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
index 65973c30f5..ac271a06bc 100644
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -46,8 +46,6 @@
#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4
#define CBMEM_ID_ROOT 0xff4007ff
#define CBMEM_ID_SMBIOS 0x534d4254
-#define CBMEM_ID_BERT_RAW_DATA 0x42455254
-#define CBMEM_ID_SMM_TSEG_SPACE 0x54534547
#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
#define CBMEM_ID_STAGEx_META 0x57a9e000
#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
@@ -113,8 +111,6 @@
{ CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \
{ CBMEM_ID_ROOT, "CBMEM ROOT " }, \
{ CBMEM_ID_SMBIOS, "SMBIOS " }, \
- { CBMEM_ID_BERT_RAW_DATA, "BERT DATA " }, \
- { CBMEM_ID_SMM_TSEG_SPACE, "TSEG " }, \
{ CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \
{ CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \
{ CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \