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authorChris Ching <chingcodes@chromium.org>2017-12-20 16:06:03 -0700
committerChris Ching <chingcodes@chromium.org>2018-01-03 22:33:49 +0000
commit6fc39d47d017409a30239a031b16413e30700452 (patch)
treef3b2a71f182ffd7982faa1fce31f93ec6f958232
parentfc511277a57857fe5fd41bf0d877d1dd17f3b92f (diff)
downloadcoreboot-6fc39d47d017409a30239a031b16413e30700452.tar.xz
soc/amd/stoneyridge: Add I2C support
BUG=b:69416132 BRANCH=none TEST=make Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/amd/stoneyridge/Kconfig5
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc4
-rw-r--r--src/soc/amd/stoneyridge/i2c.c29
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h5
-rw-r--r--src/soc/amd/stoneyridge/lpc.c6
5 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 58b940de3d..6d7039ef1c 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ACPI_AMD_HARDWARE_SLEEP_VALUES
+ select DRIVERS_I2C_DESIGNWARE
select GENERIC_GPIO_LIB
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
@@ -371,4 +372,8 @@ config RO_REGION_ONLY
depends on CHROMEOS
default "apu/amdfw"
+config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
+ int
+ default 133
+
endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 507924f2b1..87d355bd1e 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -40,6 +40,7 @@ subdirs-y += ../../../cpu/x86/smm
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += BiosCallOuts.c
bootblock-y += bootblock/bootblock.c
+bootblock-y += i2c.c
bootblock-y += pmutil.c
bootblock-y += reset.c
bootblock-y += sb_util.c
@@ -47,6 +48,7 @@ bootblock-y += tsc_freq.c
bootblock-y += southbridge.c
romstage-y += BiosCallOuts.c
+romstage-y += i2c.c
romstage-y += romstage.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
romstage-y += gpio.c
@@ -61,6 +63,7 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
+verstage-y += i2c.c
verstage-y += sb_util.c
verstage-y += pmutil.c
verstage-y += reset.c
@@ -71,6 +74,7 @@ postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
postcar-y += ramtop.c
ramstage-y += BiosCallOuts.c
+ramstage-y += i2c.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
new file mode 100644
index 0000000000..2837a910be
--- /dev/null
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/iomap.h>
+
+const uintptr_t i2c_bus_address[] = { I2C_BASE_ADDRESS,
+ I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 1,
+ I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 2,
+ I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 3,
+ };
+
+
+uintptr_t dw_i2c_base_address(unsigned int bus)
+{
+ return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
+}
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 64a9b30f2f..ac340a62af 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -22,6 +22,11 @@
#define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000
+/* I2C fixed address */
+#define I2C_BASE_ADDRESS 0xfedc2000
+#define I2C_DEVICE_SIZE 0x00001000
+#define I2C_DEVICE_COUNT 4
+
#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE)
#error HPET address override is not allowed and must be fixed at 0xfed00000
#endif
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 1e03feabb6..10f4a4b7df 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -137,6 +137,12 @@ static void lpc_read_resources(device_t dev)
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ /* I2C devices (all 4 devices) */
+ res = new_resource(dev, 4);
+ res->base = I2C_BASE_ADDRESS;
+ res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
compact_resources(dev);
/* Allocate ACPI NVS in CBMEM */