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authorTim Chen <Tim-Chen@quantatw.com>2018-02-27 19:42:46 +0800
committerMartin Roth <martinroth@google.com>2018-03-01 16:07:59 +0000
commit70ba1b7e78930acca578114cdadcbcec367730e8 (patch)
treecd65302b640e8cd4bc00adaea6b2c2ffcddecb39
parent06e3e1f055593bd2e2906f43040a703bc471cde4 (diff)
downloadcoreboot-70ba1b7e78930acca578114cdadcbcec367730e8.tar.xz
mb/google/reef: Override USB2 phy settings
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/23878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index d5f546c99b..0f11f6366c 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -116,6 +116,22 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
+ # Override USB2 PER PORT register (PORT 1)
+ register "usb2eye[1]" = "{
+ .Usb20PerPortPeTxiSet = 4,
+ .Usb20PerPortTxiSet = 4,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
+ # Override USB2 PER PORT register (PORT 4)
+ register "usb2eye[4]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 7,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF