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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 14:16:34 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-04 12:23:50 +0000
commit73a544d4533fa8305f1c0a809137b5e2151ea17e (patch)
treee7d0b63098c2d021b579599a9ce419d3ced9db52
parentc08fdf3decc6a61a9020a7df484d92473f7223e9 (diff)
downloadcoreboot-73a544d4533fa8305f1c0a809137b5e2151ea17e.tar.xz
soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function
According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/common/block/acpimmio/mmio_util.c17
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h7
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio_map.h19
-rw-r--r--src/soc/amd/picasso/southbridge.c2
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c2
5 files changed, 33 insertions, 14 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index 04d5e4af4d..a589ef549a 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -18,13 +18,22 @@
#include <amdblocks/acpimmio_map.h>
#include <amdblocks/acpimmio.h>
-void enable_acpimmio_decode(void)
+void enable_acpimmio_decode_pm24(void)
{
uint32_t dw;
- dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER);
- dw |= ACPIMMIO_DECODE_EN;
- pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw);
+ dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_24);
+ dw |= PM_24_ACPIMMIO_DECODE_EN;
+ pm_io_write32(ACPIMMIO_DECODE_REGISTER_24, dw);
+}
+
+void enable_acpimmio_decode_pm04(void)
+{
+ uint32_t dw;
+
+ dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER_04);
+ dw |= PM_04_ACPIMMIO_DECODE_EN;
+ pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw);
}
/* PM registers are accessed a byte at a time via CD6/CD7 */
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 57d24db5b2..c441ab8f63 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -101,7 +101,12 @@
*/
/* Enable the AcpiMmio range at 0xfed80000 */
-void enable_acpimmio_decode(void);
+
+/* For older discrete FCHs */
+void enable_acpimmio_decode_pm24(void);
+
+/* For newer integrated FCHs */
+void enable_acpimmio_decode_pm04(void);
/* Access PM registers using IO cycles */
uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
index 755af52d4f..9a1584004b 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -22,16 +22,21 @@
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
-/* TODO: In the event this is ported backward far enough, earlier devices
- * enable the decode in PMx24 instead. All discrete FCHs and the Kabini
- * SoC fall into this category. Kabini's successor, Mullins, uses this
- * newer method.
+/* Earlier devices enable the decode in PMx24 instead. All discrete FCHs and
+ * the Kabini SoC fall into this category. Kabini's successor, Mullins, uses
+ * this newer method.
*/
-#define ACPIMMIO_DECODE_REGISTER 0x4
-#define ACPIMMIO_DECODE_EN BIT(0)
+
+#define ACPIMMIO_DECODE_REGISTER_24 0x24
+#define PM_24_ACPIMMIO_DECODE_EN BIT(0)
+
+#define ACPIMMIO_DECODE_REGISTER_04 0x4
+#define PM_04_BIOSRAM_DECODE_EN BIT(0)
+#define PM_04_ACPIMMIO_DECODE_EN BIT(1)
+
/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled
- * in PMx24[1] (older implementations) and PMx04[1] (newer implementations).
+ * in PMx24[0] (older implementations) and PMx04[1] (newer implementations).
* PM registers are also accessible via IO CD6/CD7.
*
* All products do not support all blocks below, however AMD has avoided
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index fe801d4126..041d262af7 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -278,7 +278,7 @@ void fch_pre_init(void)
sb_disable_4dw_burst();
sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M,
SPI_SPEED_16M, SPI_SPEED_16M);
- enable_acpimmio_decode();
+ enable_acpimmio_decode_pm04();
fch_smbus_init();
sb_enable_cf9_io();
sb_enable_legacy_io();
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 8556790772..85c7eafcf1 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -399,7 +399,7 @@ void bootblock_fch_early_init(void)
lpc_enable_spi_prefetch();
sb_init_spi_base();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
- enable_acpimmio_decode();
+ enable_acpimmio_decode_pm04();
fch_smbus_init();
sb_enable_cf9_io();
setup_spread_spectrum(&reboot);