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authorDuncan Laurie <dlaurie@chromium.org>2012-01-09 22:05:18 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 17:56:10 +0200
commit7b67892be88e3f12de91314ca45a834b4c84c719 (patch)
treef7e2fadeb00c47a32adb451b81538c26280c16cc
parent527fc74a83a7b0fdeebfeb9ddd5890f11f01c102 (diff)
downloadcoreboot-7b67892be88e3f12de91314ca45a834b4c84c719.tar.xz
Make MTRR min hole alignment 64MB
This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/cpu/x86/mtrr/mtrr.c9
-rw-r--r--src/include/cpu/x86/mtrr.h3
2 files changed, 9 insertions, 3 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02bbb1..ed7d93bd06 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
return reg;
}
- if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+ if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+ range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
/*
- * If this range is not divisible by 16MB then instead
+ * If this range is not divisible then instead
* make a larger range and carve out an uncached hole.
*/
hole_startk = range_startk + range_sizek;
- hole_sizek = 0x4000 - (range_sizek % 0x4000);
+ hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
range_sizek += hole_sizek;
}
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7a3f..8b5cc281bc 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
#define MTRRdefTypeEn (1 << 11)
#define MTRRdefTypeFixEn (1 << 10)
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)