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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-01 11:10:37 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-13 19:20:22 +0000 |
| commit | 7bc0e4274928243df61e96a099d141d7251a3956 (patch) | |
| tree | e876744ff85db62d3ee9c57962b18577426bbbaa | |
| parent | f796dd86a79831f97bdb61ad7f29f140b8b941a5 (diff) | |
| download | coreboot-7bc0e4274928243df61e96a099d141d7251a3956.tar.xz | |
amd/stoneyridge: Remove duplicate PCI definitions
There were two copies of the same definitions in the file.
Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/pci_devs.h | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 5c7f86a8c7..caa4765b1c 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -19,48 +19,6 @@ #include <device/pci_def.h> #include <rules.h> -/* HT Configuration */ -#define HT_DEV 0x18 -#define HT_FUNC 0 -#define HT_DEVID 0x15b0 -#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) - -/* Address Maps */ -#define ADDR_DEV 0x18 -#define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 -#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) - -/* DRAM Configuration */ -#define DCT_DEV 0x18 -#define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 -#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) - -/* Misc. Configuration */ -#define MISC_DEV 0x18 -#define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 -#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) - -/* PM Configuration */ -#define PM_DEV 0x18 -#define PM_FUNC 4 -#define PM_DEVID 0x15b4 -#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) -#if !defined(__SIMPLE_DEVICE__) - #include <device/device.h> - #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) -#else - #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC) -#endif - -/* Northbridge Configuration */ -#define NB_DEV 0x18 -#define NB_FUNC 5 -#define NB_DEVID 0x15b5 -#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) - /* GNB Root Complex */ #define GNB_DEV 0x0 #define GNB_FUNC 0 |