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| author | John Zhao <john.zhao@intel.com> | 2021-05-13 23:08:16 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-18 21:59:33 +0000 |
| commit | 7e982b1dd9de4c8a4a534588f18d5e429389e52e (patch) | |
| tree | 9c2cd525ea81a56c13476f2aaa8d38345d713fc1 | |
| parent | d4717cf3a4c49cdd467a8078a4a387d154c13a95 (diff) | |
| download | coreboot-7e982b1dd9de4c8a4a534588f18d5e429389e52e.tar.xz | |
mb/intel/shadowmountain: Update mainboard properties
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
BUG=b:186521258
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 4289a4b624..43a23a19c4 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -188,7 +188,14 @@ chip soc/intel/alderlake device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 + device pci 0d.2 on + chip drivers/intel/usb4/retimer + register "dfp" = "{ + [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),}, + [1] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),}}" + device generic 0 on end + end + end device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end |