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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-26 14:42:52 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-04 21:09:20 +0000 |
| commit | 812f36425e79e202d38c1bab16eef261ea2fb417 (patch) | |
| tree | f67bc8b882229efe1c6a846f17beeb5228cced0c | |
| parent | bca5bdb05661d5874d3c4b6de6a6f5a3fe5dc6cc (diff) | |
| download | coreboot-812f36425e79e202d38c1bab16eef261ea2fb417.tar.xz | |
mb/google/brya: Set UART console
Follow latest schematic UART_PCH_DBG is UART 0.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e448e18e21..4a9f2e15b1 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_BRYA select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ALDERLAKE if BOARD_GOOGLE_BASEBOARD_BRYA @@ -31,4 +32,8 @@ config VARIANT_DIR string default "brya0" if BOARD_GOOGLE_BRYA0 +config UART_FOR_CONSOLE + int + default 0 + endif # BOARD_GOOGLE_BASEBOARD_BRYA |