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authorShelley Chen <shchen@chromium.org>2018-01-22 10:26:31 -0800
committerShelley Chen <shchen@google.com>2018-01-23 18:52:43 +0000
commit8bd8cd3a222bb8d54fd2510728c87dc6909b287c (patch)
tree3041832b3e1ffabf546db7d5ce812ac3a3bea94a
parent65d2754e1aaa4e90059b65fac3c00d847e2e465f (diff)
downloadcoreboot-8bd8cd3a222bb8d54fd2510728c87dc6909b287c.tar.xz
mainboard/google/fizz: Tune audio i2c parameters
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/fizz/devicetree.cb11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 81b5dc5603..8cf4e52fb9 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -247,6 +247,17 @@ chip soc/intel/skylake
.early_init = 1,
}"
+ # audio
+ register "i2c[5]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 194,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ }"
+
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,