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authorJonathan A. Kollasch <jakllsch@kollasch.net>2011-08-03 13:56:24 -0500
committerPatrick Georgi <patrick@georgi-clan.de>2011-08-03 21:28:14 +0200
commit8e9f156f482be2739926ef2ec82d2140384e6de9 (patch)
tree927d413e493c0cc0e1715473276f333fe06ec7c8
parentc2ffc6739cd94d996e8c11669031c101455eab90 (diff)
downloadcoreboot-8e9f156f482be2739926ef2ec82d2140384e6de9.tar.xz
Remove debugging code, or convert it to be selected by kconfig
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
-rw-r--r--src/mainboard/msi/ms7135/romstage.c11
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 5feef79625..80b3c19bde 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -112,10 +112,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
@@ -140,17 +136,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
-#if 0
+#if CONFIG_DEBUG_SMBUS
dump_spd_registers(&ctrl[0]);
dump_smbus_registers();
#endif
sdram_initialize(nodes, ctrl);
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-
post_cache_as_ram();
}