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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-04 16:20:54 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-20 09:19:20 +0000 |
| commit | 8f3e1192dfe5e3008524b587de4f06a0f289b646 (patch) | |
| tree | 8a0b0542ad24a7d93ee14f067d1e0525c0451368 | |
| parent | dfe3a2fcfca5ade7d82ed7e92758e5f329c28880 (diff) | |
| download | coreboot-8f3e1192dfe5e3008524b587de4f06a0f289b646.tar.xz | |
soc/intel/skylake: Move `SataTestMode` to Kconfig
This option is not mainboard-specific, and should be user-visible.
Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
| -rw-r--r-- | src/mainboard/hp/280_g2/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
4 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 8784080f95..98fccc972d 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -75,9 +75,6 @@ chip soc/intel/skylake [3] = 1, }" # DevSlp not supported - - # Enable test mode for SATA margining - register "SataTestMode" = "1" end device pci 19.0 on end # UART #2 device pci 1c.0 off end # RP #1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 29f8159fcf..5024ef455b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -91,6 +91,12 @@ config FSP_HYPERTHREADING bool "Enable Hyper-Threading" default y +config ENABLE_SATA_TEST_MODE + bool "Enable SATA test mode" + default n + help + Enable SATA test mode in FSP-S. + config CPU_INTEL_NUM_FIT_ENTRIES int default 10 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d4d8938d8f..d4e8341cdc 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -304,7 +304,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * write" errors and others. Enabling this option solves these problems. */ params->SataPwrOptEnable = 1; - tconfig->SataTestMode = config->SataTestMode; + tconfig->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE); } memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1c8ca49632..d30547ec26 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -477,9 +477,6 @@ struct soc_intel_skylake_config { */ u8 IslVrCmd; - /* Enable/Disable Sata test mode */ - u8 SataTestMode; - /* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; }; |