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authorJulius Werner <jwerner@chromium.org>2014-12-17 17:38:38 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-15 16:31:41 +0200
commit908ceefd25ffd6427c3a53502598006bacf22750 (patch)
treed0d7c1de246c17e70b27ab0708dd1676fb123041
parent3cbf02cc8897ab5c90c3a06f6e8121ce09c243a5 (diff)
downloadcoreboot-908ceefd25ffd6427c3a53502598006bacf22750.tar.xz
veyron: Fix TPM I2C initialization and sync boards
Due to a missing i2c_init(), we were actually running our TPM with default divisors at 660KHz. Oops. While it's commendable that both the TPM and our controller seem to have been running fine all this time at more than 1.5 times the maximum frequency they support, we should probably still get that fixed. Also sync Speedy back up to the other Veyron boards since it seems to have missed a recent SDMMC patch. BRANCH=None BUG=None TEST=Booted Pinky. Change-Id: I255c66624b21bf48b12f950208ba2c401a75c4e4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f2bd7c8579cd90d2f800c777c1981557d81a9b49 Original-Change-Id: I43e6b5fe02aca605a5b243c5b876bd44b90b2bf9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236580 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9634 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r--src/mainboard/google/veyron_jerry/bootblock.c1
-rw-r--r--src/mainboard/google/veyron_jerry/mainboard.c6
-rw-r--r--src/mainboard/google/veyron_mighty/bootblock.c1
-rw-r--r--src/mainboard/google/veyron_mighty/mainboard.c6
-rw-r--r--src/mainboard/google/veyron_pinky/bootblock.c1
-rw-r--r--src/mainboard/google/veyron_pinky/mainboard.c6
-rw-r--r--src/mainboard/google/veyron_speedy/bootblock.c1
-rw-r--r--src/mainboard/google/veyron_speedy/mainboard.c7
-rw-r--r--src/mainboard/google/veyron_speedy/romstage.c12
9 files changed, 20 insertions, 21 deletions
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 4536f31069..5571d456f8 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -64,6 +64,7 @@ void bootblock_mainboard_init(void)
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
index 9d8bb5d6dd..d9952605dc 100644
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ b/src/mainboard/google/veyron_jerry/mainboard.c
@@ -72,7 +72,7 @@ static void configure_emmc(void)
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
- i2c_init(2, 400000); /* CODEC I2C */
+ i2c_init(2, 400*KHz); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
@@ -108,10 +108,6 @@ static void configure_vop(void)
static void mainboard_init(device_t dev)
{
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */
- i2c_init(0, 400000); /* PMIC I2C */
-
gpio_output(GPIO_RESET, 0);
configure_usb();
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 4536f31069..5571d456f8 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -64,6 +64,7 @@ void bootblock_mainboard_init(void)
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
index dd2274840e..c7d51cc948 100644
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ b/src/mainboard/google/veyron_mighty/mainboard.c
@@ -72,7 +72,7 @@ static void configure_emmc(void)
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
- i2c_init(2, 400000); /* CODEC I2C */
+ i2c_init(2, 400*KHz); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
@@ -108,10 +108,6 @@ static void configure_vop(void)
static void mainboard_init(device_t dev)
{
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */
- i2c_init(0, 400000); /* PMIC I2C */
-
gpio_output(GPIO_RESET, 0);
configure_usb();
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 4536f31069..5571d456f8 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -64,6 +64,7 @@ void bootblock_mainboard_init(void)
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index 4752547f6f..0266965753 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -103,7 +103,7 @@ static void configure_emmc(void)
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
- i2c_init(2, 400000); /* CODEC I2C */
+ i2c_init(2, 400*KHz); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
@@ -152,10 +152,6 @@ static void configure_vop(void)
static void mainboard_init(device_t dev)
{
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */
- i2c_init(0, 400000); /* PMIC I2C */
-
gpio_output(GPIO_RESET, 0);
configure_usb();
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 4536f31069..5571d456f8 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -64,6 +64,7 @@ void bootblock_mainboard_init(void)
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
index 73595d79c1..8efc65d4dd 100644
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ b/src/mainboard/google/veyron_speedy/mainboard.c
@@ -53,6 +53,7 @@ static void configure_sdmmc(void)
/* use sdmmc0 io, disable JTAG function */
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ /* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
@@ -71,7 +72,7 @@ static void configure_emmc(void)
static void configure_codec(void)
{
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
- i2c_init(2, 400000); /* CODEC I2C */
+ i2c_init(2, 400*KHz); /* CODEC I2C */
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
@@ -97,10 +98,6 @@ static void configure_vop(void)
static void mainboard_init(device_t dev)
{
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); /* PMIC I2C */
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); /* PMIC I2C */
- i2c_init(0, 400000); /* PMIC I2C */
-
gpio_output(GPIO_RESET, 0);
configure_usb();
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c
index 201931968a..2dec53c332 100644
--- a/src/mainboard/google/veyron_speedy/romstage.c
+++ b/src/mainboard/google/veyron_speedy/romstage.c
@@ -32,6 +32,7 @@
#include <soc/clock.h>
#include <soc/pwm.h>
#include <soc/grf.h>
+#include <soc/rk808.h>
#include <soc/tsadc.h>
#include <stdlib.h>
#include <symbols.h>
@@ -39,7 +40,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include "timer.h"
+#include "board.h"
static void regulate_vdd_log(unsigned int mv)
{
@@ -77,6 +78,12 @@ static void configure_l2ctlr(void)
write_l2ctlr(l2ctlr);
}
+static void sdmmc_power_off(void)
+{
+ rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
+ rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
+}
+
void main(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
@@ -91,6 +98,9 @@ void main(void)
configure_l2ctlr();
tsadc_init();
+ /* Need to power cycle SD card to ensure it is properly reset. */
+ sdmmc_power_off();
+
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS