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authorRaul E Rangel <rrangel@chromium.org>2020-09-23 12:10:02 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-09-28 09:39:49 +0000
commit96c704a16729243469e01b587ea5f3eab9ab1213 (patch)
tree4289ec6c81d0a3f603a5c676a4952aa24e4dbda0
parent94be1f7399629de0578c56625ddd327cc1123fe4 (diff)
downloadcoreboot-96c704a16729243469e01b587ea5f3eab9ab1213.tar.xz
soc/amd/picasso: Set eMMC preset UPDs
Now that all boards have bootable driver strengths and init frequency, we can pass them to FSP. BUG=b:159823235 TEST=Boot ezkinil to kernel and print presets. SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x3ff: SdClkFreq SDHC0x8F2 Default Speed 3.3V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8F4 High Speed 3.3V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8F6 SDR12 1.8V => 0x0008 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x8: SdClkFreq SDHC0x8F8 SDR25 1.8V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8FA SDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8FC SDR104 1.8V => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq SDHC0x8FE DDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x900 HS400 => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
-rw-r--r--src/soc/amd/picasso/fsp_params.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index b21f237c32..95e691dc5d 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -55,6 +55,11 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
}
scfg->emmc0_mode = val;
+ scfg->emmc0_sdr104_hs400_driver_strength =
+ cfg->emmc_config.sdr104_hs400_driver_strength;
+ scfg->emmc0_ddr50_driver_strength = cfg->emmc_config.ddr50_driver_strength;
+ scfg->emmc0_sdr50_driver_strength = cfg->emmc_config.sdr50_driver_strength;
+ scfg->emmc0_init_khz_preset = cfg->emmc_config.init_khz_preset;
}
static void fill_dxio_descriptors(FSP_S_CONFIG *scfg,