summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-02-11 11:39:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-02-13 13:02:06 +0000
commit97b30d86592af6bbf26f9c9bcaf95f13d5cab9ce (patch)
tree86296892cae161c4e044e0cd9f457365f2226c86
parent1a8387eabadb16adae2b5a032611813587957ed5 (diff)
downloadcoreboot-97b30d86592af6bbf26f9c9bcaf95f13d5cab9ce.tar.xz
cpu/intel/common: Add Nehalem for FSB detection
Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31339 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/intel/common/fsb.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 92967859dd..83220de3bc 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -39,8 +39,11 @@ static int get_fsb(void)
case 0x17: /* Enhanced Core */
ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
- case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
- case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+ case 0x25: /* Nehalem BCLK fixed at 133MHz */
+ ret = 133;
+ break;
+ case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
+ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
ret = 100;