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authorNico Huber <nico.huber@secunet.com>2017-07-19 15:45:14 +0200
committerNico Huber <nico.h@gmx.de>2017-07-20 15:44:59 +0000
commit9dc62ea133d826cf88ccd29e579ea976257d5487 (patch)
treef162714260ea26cbf2637cde5bd4e39fecc800d5
parentfb66e81e6c58b0825e85b2c0afabbe032f103d6e (diff)
downloadcoreboot-9dc62ea133d826cf88ccd29e579ea976257d5487.tar.xz
soc/intel/skylake: Fix broken memory info HOB scanning
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 9e871254cb..e439d73479 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -79,17 +79,15 @@ static void save_dimm_info(void)
index = 0;
dimm_max = ARRAY_SIZE(mem_info->dimm);
ctrlr_info = &memory_info_hob->Controller[0];
- for (channel = 0; channel < ctrlr_info->ChannelCount; channel++) {
- if (index >= dimm_max)
- break;
+ for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
channel_info = &ctrlr_info->Channel[channel];
- for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
- if (index >= dimm_max)
- break;
+ if (channel_info->Status != 2)
+ continue;
+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
src_dimm = &channel_info->Dimm[dimm];
dest_dimm = &mem_info->dimm[index];
- if (!src_dimm->DimmCapacity)
+ if (src_dimm->Status != DIMM_PRESENT)
continue;
/* Populate the DIMM information */