diff options
| author | Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> | 2020-12-23 11:45:59 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-01-01 02:58:33 +0000 |
| commit | 9e38efc27be1e5561da611b1e570ef3a52529da2 (patch) | |
| tree | 6d4ecc1c053638cc5731140810d26181ff18cca5 | |
| parent | b32e4d67637f6b9dd9c46309ca623d80465a561f (diff) | |
| download | coreboot-9e38efc27be1e5561da611b1e570ef3a52529da2.tar.xz | |
soc/mediatek: dsi: Fix EoTp flag
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.
Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.
BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/soc/mediatek/common/dsi.c | 11 | ||||
| -rw-r--r-- | src/soc/mediatek/common/include/soc/dsi_common.h | 6 |
2 files changed, 15 insertions, 2 deletions
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2505bbc075..8254dc5e87 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -154,8 +154,11 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) break; } - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + tmp_reg |= NON_CONTINUOUS_CLK; + + if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET)) + tmp_reg |= EOTP_DISABLE; write32(&dsi0->dsi_txrx_ctrl, tmp_reg); } @@ -202,6 +205,10 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; u32 delta = 12; + + if (mode_flags & MIPI_DSI_MODE_EOT_PACKET) + delta += 2; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) delta += 6; diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7bacec1c77..aebe62aa36 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -118,6 +118,12 @@ enum { MIX_MODE = BIT(17) }; +/* DSI_TXRX_CTRL */ +enum { + EOTP_DISABLE = BIT(6), + NON_CONTINUOUS_CLK = BIT(16), +}; + /* DSI_PSCTRL */ enum { DSI_PS_WC = 0x3fff, |