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authorAngel Pons <th3fanbus@gmail.com>2020-09-14 13:15:19 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-17 19:57:50 +0000
commita3cb3220185cf47a59a1b8b74d3a4fcdef5e57b6 (patch)
tree4593ab28dc190ddf1a0eaa2e9e77665d04633bfe
parent743159396ad8c8697187e823d5ff069336a18080 (diff)
downloadcoreboot-a3cb3220185cf47a59a1b8b74d3a4fcdef5e57b6.tar.xz
nb/intel/haswell: Introduce memmap.h
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib275f9ad8ca9ff343604c9e8cbb130c74ddad54f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45351 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/northbridge/intel/haswell/haswell.h14
-rw-r--r--src/northbridge/intel/haswell/memmap.h20
2 files changed, 21 insertions, 13 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 9a99c2abc5..00cc885c9c 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -8,19 +8,7 @@
#define HASWELL_DESKTOP 1
#define HASWELL_SERVER 2
-/* Intel Enhanced Debug region */
-#define IED_SIZE CONFIG_IED_REGION_SIZE
-
-/* Northbridge BARs */
-#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
-#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
-#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-
-#define GFXVT_BASE_ADDRESS 0xfed90000ULL
-#define GFXVT_BASE_SIZE 0x1000
-
-#define VTVC0_BASE_ADDRESS 0xfed91000ULL
-#define VTVC0_BASE_SIZE 0x1000
+#include "memmap.h"
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h
new file mode 100644
index 0000000000..ac3b1dbef0
--- /dev/null
+++ b/src/northbridge/intel/haswell/memmap.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__
+#define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__
+
+/* Intel Enhanced Debug region */
+#define IED_SIZE CONFIG_IED_REGION_SIZE
+
+/* Northbridge BARs */
+#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+
+#define GFXVT_BASE_ADDRESS 0xfed90000ULL
+#define GFXVT_BASE_SIZE 0x1000
+
+#define VTVC0_BASE_ADDRESS 0xfed91000ULL
+#define VTVC0_BASE_SIZE 0x1000
+
+#endif /* __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ */