diff options
| author | Scott Duplichan <scott@notabs.org> | 2011-05-15 21:01:42 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-05-15 21:01:42 +0000 |
| commit | a72425a7e624efd01bacbea87154383b05e41b57 (patch) | |
| tree | 24f3db823bde8c0039bdc1f5c8b3ad91fae049b3 | |
| parent | eb97e9688f4ae8060c12cd1c57c3bc80c547e5b2 (diff) | |
| download | coreboot-a72425a7e624efd01bacbea87154383b05e41b57.tar.xz | |
1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/cpu/amd/agesa_wrapper/family14/model_14_init.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/cpu/amd/agesa_wrapper/family14/model_14_init.c b/src/cpu/amd/agesa_wrapper/family14/model_14_init.c index 01bd2639f0..d4d9667908 100644 --- a/src/cpu/amd/agesa_wrapper/family14/model_14_init.c +++ b/src/cpu/amd/agesa_wrapper/family14/model_14_init.c @@ -62,6 +62,7 @@ static void model_14_init(device_t dev) u8 i; msr_t msr; + int msrno; struct node_core_id id; #if CONFIG_LOGICAL_CPUS == 1 u32 siblings; @@ -70,12 +71,24 @@ static void model_14_init(device_t dev) // id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */ // printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid); - /* Turn on caching if we haven't already */ - x86_enable_cache(); - amd_setup_mtrrs(); - x86_mtrr_check(); - - disable_cache(); + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); /* zero the machine check error status registers */ msr.lo = 0; @@ -84,8 +97,6 @@ static void model_14_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - enable_cache(); - /* Enable the local cpu apics */ setup_lapic(); |