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authorJohn Zhao <john.zhao@intel.com>2021-05-13 21:07:47 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-18 21:58:36 +0000
commita7f8fb59e560b8b5e32d5241942c21bd2fa00f20 (patch)
tree6eb8a3aa9b4fac35d8c2bb0a0abf001e5a81964d
parentbc9ab1785212c4bb18ffdca74569edf5c47378c2 (diff)
downloadcoreboot-a7f8fb59e560b8b5e32d5241942c21bd2fa00f20.tar.xz
mb/intel/shadowmountain: Remove power_gpio from baseboard
Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 55d250539c..4289a4b624 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -188,12 +188,7 @@ chip soc/intel/alderlake
device pci 0a.0 off end # Crash-log SRAM
device pci 0d.0 on end # USB xHCI
device pci 0d.1 off end # USB xDCI (OTG)
- device pci 0d.2 on
- chip drivers/intel/usb4/retimer
- register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19)"
- device generic 0 on end
- end
- end
+ device pci 0d.2 on end # TBT DMA0
device pci 0d.3 on end # TBT DMA1
device pci 0e.0 off end # VMD
device pci 10.0 off end