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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-21 00:16:06 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-21 00:16:06 +0000
commitb5e10bcf1fdaa684189581b65861ab6f7775c4f1 (patch)
tree86672cc3153a39c113c2a9e6f6918716d6fda5be
parent108950972504f37cc354f79a0aa0895eae751523 (diff)
downloadcoreboot-b5e10bcf1fdaa684189581b65861ab6f7775c4f1.tar.xz
Thanks to Myles' patch adding support for include statements,
refactoring Config.lb became possible. Factor out ROM size calculation from Config.lb. This patch converts 87 boards (with and without USE_FAILOVER_IMAGE), but it has to work around a parser bug. 89 files changed, 209 insertions(+), 2415 deletions(-) A total of 2206 removed lines. Abuild works for all changed boards on khepri. Myles writes: I've tested serengeti for the failover portion and s2892 for the nofailover portion. ldoptions are exactly the same and they both boot the same. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/a-trend/atc-6220/Config.lb15
-rw-r--r--src/mainboard/a-trend/atc-6240/Config.lb15
-rw-r--r--src/mainboard/abit/be6-ii_v2_0/Config.lb15
-rw-r--r--src/mainboard/advantech/pcm-5820/Config.lb15
-rw-r--r--src/mainboard/amd/db800/Config.lb36
-rw-r--r--src/mainboard/amd/dbm690t/Config.lb35
-rw-r--r--src/mainboard/amd/norwich/Config.lb36
-rw-r--r--src/mainboard/amd/pistachio/Config.lb35
-rw-r--r--src/mainboard/amd/rumba/Config.lb34
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Config.lb48
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/Config.lb48
-rw-r--r--src/mainboard/artecgroup/dbe61/Config.lb34
-rw-r--r--src/mainboard/asi/mb_5blgp/Config.lb15
-rw-r--r--src/mainboard/asi/mb_5blmp/Config.lb34
-rw-r--r--src/mainboard/asus/a8n_e/Config.lb29
-rw-r--r--src/mainboard/asus/a8v-e_se/Config.lb16
-rw-r--r--src/mainboard/asus/mew-am/Config.lb15
-rw-r--r--src/mainboard/asus/mew-vm/Config.lb34
-rw-r--r--src/mainboard/asus/p2b-d/Config.lb15
-rw-r--r--src/mainboard/asus/p2b-ds/Config.lb15
-rw-r--r--src/mainboard/asus/p2b-f/Config.lb15
-rw-r--r--src/mainboard/asus/p2b/Config.lb15
-rw-r--r--src/mainboard/asus/p3b-f/Config.lb15
-rw-r--r--src/mainboard/axus/tc320/Config.lb15
-rw-r--r--src/mainboard/azza/pt-6ibd/Config.lb14
-rw-r--r--src/mainboard/bcom/winnet100/Config.lb14
-rw-r--r--src/mainboard/bcom/winnetp680/Config.lb14
-rw-r--r--src/mainboard/biostar/m6tba/Config.lb15
-rw-r--r--src/mainboard/broadcom/blast/Config.lb34
-rw-r--r--src/mainboard/compaq/deskpro_en_sff_p600/Config.lb15
-rw-r--r--src/mainboard/digitallogic/adl855pc/Config.lb34
-rw-r--r--src/mainboard/digitallogic/msm800sev/Config.lb34
-rw-r--r--src/mainboard/eaglelion/5bcm/Config.lb34
-rw-r--r--src/mainboard/gigabyte/ga-6bxc/Config.lb15
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/Config.lb48
-rw-r--r--src/mainboard/gigabyte/m57sli/Config.lb48
-rw-r--r--src/mainboard/ibm/e325/Config.lb34
-rw-r--r--src/mainboard/ibm/e326/Config.lb34
-rw-r--r--src/mainboard/iei/nova4899r/Config.lb34
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/Config.lb14
-rw-r--r--src/mainboard/iwill/dk8_htx/Config.lb48
-rw-r--r--src/mainboard/iwill/dk8s2/Config.lb34
-rw-r--r--src/mainboard/iwill/dk8x/Config.lb34
-rw-r--r--src/mainboard/jetway/j7f24/Config.lb14
-rw-r--r--src/mainboard/lippert/frontrunner/Config.lb34
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Config.lb36
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Config.lb35
-rw-r--r--src/mainboard/msi/ms6119/Config.lb15
-rw-r--r--src/mainboard/msi/ms6147/Config.lb16
-rw-r--r--src/mainboard/msi/ms6178/Config.lb14
-rw-r--r--src/mainboard/msi/ms7135/Config.lb47
-rw-r--r--src/mainboard/msi/ms7260/Config.lb28
-rw-r--r--src/mainboard/msi/ms9185/Config.lb34
-rw-r--r--src/mainboard/msi/ms9282/Config.lb36
-rw-r--r--src/mainboard/nec/powermate2000/Config.lb14
-rw-r--r--src/mainboard/newisys/khepri/Config.lb34
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Config.lb48
-rw-r--r--src/mainboard/olpc/btest/Config.lb34
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb34
-rw-r--r--src/mainboard/pcengines/alix1c/Config.lb34
-rw-r--r--src/mainboard/rca/rm4100/Config.lb14
-rw-r--r--src/mainboard/sunw/ultra40/Config.lb36
-rw-r--r--src/mainboard/supermicro/h8dme/Config.lb48
-rw-r--r--src/mainboard/supermicro/h8dmr/Config.lb48
-rw-r--r--src/mainboard/technexion/tim8690/Config.lb35
-rw-r--r--src/mainboard/televideo/tc7020/Config.lb14
-rw-r--r--src/mainboard/thomson/ip1000/Config.lb14
-rw-r--r--src/mainboard/tyan/s1846/Config.lb15
-rw-r--r--src/mainboard/tyan/s2735/Config.lb36
-rw-r--r--src/mainboard/tyan/s2850/Config.lb34
-rw-r--r--src/mainboard/tyan/s2875/Config.lb34
-rw-r--r--src/mainboard/tyan/s2880/Config.lb34
-rw-r--r--src/mainboard/tyan/s2881/Config.lb34
-rw-r--r--src/mainboard/tyan/s2882/Config.lb34
-rw-r--r--src/mainboard/tyan/s2885/Config.lb34
-rw-r--r--src/mainboard/tyan/s2891/Config.lb35
-rw-r--r--src/mainboard/tyan/s2892/Config.lb36
-rw-r--r--src/mainboard/tyan/s2895/Config.lb48
-rw-r--r--src/mainboard/tyan/s2912/Config.lb48
-rw-r--r--src/mainboard/tyan/s2912_fam10/Config.lb48
-rw-r--r--src/mainboard/tyan/s4880/Config.lb36
-rw-r--r--src/mainboard/tyan/s4882/Config.lb36
-rw-r--r--src/mainboard/via/epia-cn/Config.lb14
-rw-r--r--src/mainboard/via/epia-m/Config.lb34
-rw-r--r--src/mainboard/via/epia/Config.lb34
-rw-r--r--src/mainboard/via/pc2500e/Config.lb14
-rw-r--r--src/mainboard/via/vt8454c/Config.lb34
87 files changed, 123 insertions, 2415 deletions
diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb
index f8c18aaf8d..ff46309e2f 100644
--- a/src/mainboard/a-trend/atc-6220/Config.lb
+++ b/src/mainboard/a-trend/atc-6220/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb
index 2cb5ab724f..a9d09ef093 100644
--- a/src/mainboard/a-trend/atc-6240/Config.lb
+++ b/src/mainboard/a-trend/atc-6240/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb
index 94da361f09..e2799967af 100644
--- a/src/mainboard/abit/be6-ii_v2_0/Config.lb
+++ b/src/mainboard/abit/be6-ii_v2_0/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb
index 9029973299..ad0464c5db 100644
--- a/src/mainboard/advantech/pcm-5820/Config.lb
+++ b/src/mainboard/advantech/pcm-5820/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb
index 8ff990d0bf..06b049cedc 100644
--- a/src/mainboard/amd/db800/Config.lb
+++ b/src/mainboard/amd/db800/Config.lb
@@ -1,38 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
index 93dc5be88b..9ed0a3ac94 100644
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ b/src/mainboard/amd/dbm690t/Config.lb
@@ -19,40 +19,7 @@
##
##
-
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb
index a202fcc3fd..62b13ec97f 100644
--- a/src/mainboard/amd/norwich/Config.lb
+++ b/src/mainboard/amd/norwich/Config.lb
@@ -1,38 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb
index 753ba1df3e..20d33782f3 100644
--- a/src/mainboard/amd/pistachio/Config.lb
+++ b/src/mainboard/amd/pistachio/Config.lb
@@ -19,40 +19,7 @@
##
##
-
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
index 4ffb3b2046..156da69b51 100644
--- a/src/mainboard/amd/rumba/Config.lb
+++ b/src/mainboard/amd/rumba/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
index 0abbcd28a9..0cd264ff6c 100644
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Config.lb
@@ -1,50 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
index 1ba19572fe..02ef9f9391 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
@@ -17,53 +17,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-#
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
index 2843c40e82..be488c5a98 100644
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ b/src/mainboard/artecgroup/dbe61/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb
index d25a22f526..8ad3ed9723 100644
--- a/src/mainboard/asi/mb_5blgp/Config.lb
+++ b/src/mainboard/asi/mb_5blgp/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb
index 8762641f44..7bfcd6057d 100644
--- a/src/mainboard/asi/mb_5blmp/Config.lb
+++ b/src/mainboard/asi/mb_5blmp/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
index 092deaf579..5f4b22602e 100644
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ b/src/mainboard/asus/a8n_e/Config.lb
@@ -21,33 +21,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- default ROM_SECTION_OFFSET = 0
- end
-end
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-# XIP_ROM_SIZE must be a power of 2.
-# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE.
-default XIP_ROM_SIZE = 64 * 1024
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
+
arch i386 end
driver mainboard.o
# Needed by irq_tables and mptable and acpi_tables.
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
index ea19347d07..d9327a6735 100644
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ b/src/mainboard/asus/a8v-e_se/Config.lb
@@ -20,20 +20,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb
index 78c5c2f3ed..5da36c7dc2 100644
--- a/src/mainboard/asus/mew-am/Config.lb
+++ b/src/mainboard/asus/mew-am/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
index 997b71d82d..a4a061bbe1 100644
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ b/src/mainboard/asus/mew-vm/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb
index 2500fda238..7fc93c5c0b 100644
--- a/src/mainboard/asus/p2b-d/Config.lb
+++ b/src/mainboard/asus/p2b-d/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb
index fc87b66886..9a53045f5d 100644
--- a/src/mainboard/asus/p2b-ds/Config.lb
+++ b/src/mainboard/asus/p2b-ds/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb
index 660022df6d..50c7bc3e5e 100644
--- a/src/mainboard/asus/p2b-f/Config.lb
+++ b/src/mainboard/asus/p2b-f/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb
index 0e52732b90..b46e85aff1 100644
--- a/src/mainboard/asus/p2b/Config.lb
+++ b/src/mainboard/asus/p2b/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb
index 6799150d1e..cec443a35b 100644
--- a/src/mainboard/asus/p3b-f/Config.lb
+++ b/src/mainboard/asus/p3b-f/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb
index c6561c024b..599b7cbc40 100644
--- a/src/mainboard/axus/tc320/Config.lb
+++ b/src/mainboard/axus/tc320/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb
index ba9170f5d5..4a9ee3ee1e 100644
--- a/src/mainboard/azza/pt-6ibd/Config.lb
+++ b/src/mainboard/azza/pt-6ibd/Config.lb
@@ -18,19 +18,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb
index 4b03d9f3e4..144075891b 100644
--- a/src/mainboard/bcom/winnet100/Config.lb
+++ b/src/mainboard/bcom/winnet100/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb
index 5c2ac503c1..e7f1b929ea 100644
--- a/src/mainboard/bcom/winnetp680/Config.lb
+++ b/src/mainboard/bcom/winnetp680/Config.lb
@@ -19,18 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb
index 571c6b38a8..d3e7f967a3 100644
--- a/src/mainboard/biostar/m6tba/Config.lb
+++ b/src/mainboard/biostar/m6tba/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb
index f782d27d9c..4b8b016dcf 100644
--- a/src/mainboard/broadcom/blast/Config.lb
+++ b/src/mainboard/broadcom/blast/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
index 2536aee64c..c037b6f3cc 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
index a6680444a0..55068cfda1 100644
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ b/src/mainboard/digitallogic/adl855pc/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
index 47ac935f1c..3bc9d5b26e 100644
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ b/src/mainboard/digitallogic/msm800sev/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb
index 595845c7b9..2f11571d9c 100644
--- a/src/mainboard/eaglelion/5bcm/Config.lb
+++ b/src/mainboard/eaglelion/5bcm/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb
index 984b1b4986..1ff089cafa 100644
--- a/src/mainboard/gigabyte/ga-6bxc/Config.lb
+++ b/src/mainboard/gigabyte/ga-6bxc/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index 62e8994a54..1d92db0355 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -21,53 +21,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index 4bbdfcf463..0a72cddbe6 100644
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -19,53 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb
index e3c51cb9ee..79ac0dcfd4 100644
--- a/src/mainboard/ibm/e325/Config.lb
+++ b/src/mainboard/ibm/e325/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/ibm/e326/Config.lb b/src/mainboard/ibm/e326/Config.lb
index ac948d8e62..ef6a5a2d8e 100644
--- a/src/mainboard/ibm/e326/Config.lb
+++ b/src/mainboard/ibm/e326/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb
index ef36ac1621..152f428dff 100644
--- a/src/mainboard/iei/nova4899r/Config.lb
+++ b/src/mainboard/iei/nova4899r/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
index 0a7e33d1a7..cfa20044e7 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
index 11ed24d347..2ef37975af 100644
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ b/src/mainboard/iwill/dk8_htx/Config.lb
@@ -1,50 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb
index ed9ebc729c..f18111657a 100644
--- a/src/mainboard/iwill/dk8s2/Config.lb
+++ b/src/mainboard/iwill/dk8s2/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb
index 130624bad2..912271a881 100644
--- a/src/mainboard/iwill/dk8x/Config.lb
+++ b/src/mainboard/iwill/dk8x/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb
index f665fdbf44..88b2e97430 100644
--- a/src/mainboard/jetway/j7f24/Config.lb
+++ b/src/mainboard/jetway/j7f24/Config.lb
@@ -19,18 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb
index 7dfa0ac556..6859b6a4fa 100644
--- a/src/mainboard/lippert/frontrunner/Config.lb
+++ b/src/mainboard/lippert/frontrunner/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
index 48436c62a1..d47b5c1897 100644
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ b/src/mainboard/lippert/roadrunner-lx/Config.lb
@@ -20,41 +20,7 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb
index 8ea92d01e8..98c3b22095 100644
--- a/src/mainboard/lippert/spacerunner-lx/Config.lb
+++ b/src/mainboard/lippert/spacerunner-lx/Config.lb
@@ -20,40 +20,7 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/msi/ms6119/Config.lb b/src/mainboard/msi/ms6119/Config.lb
index a03cd1eaf2..f97add2255 100644
--- a/src/mainboard/msi/ms6119/Config.lb
+++ b/src/mainboard/msi/ms6119/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/msi/ms6147/Config.lb b/src/mainboard/msi/ms6147/Config.lb
index 1d18b048d1..d7c99a315c 100644
--- a/src/mainboard/msi/ms6147/Config.lb
+++ b/src/mainboard/msi/ms6147/Config.lb
@@ -18,21 +18,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
arch i386 end
driver mainboard.o
diff --git a/src/mainboard/msi/ms6178/Config.lb b/src/mainboard/msi/ms6178/Config.lb
index ec9509b2de..bfaf8f6f43 100644
--- a/src/mainboard/msi/ms6178/Config.lb
+++ b/src/mainboard/msi/ms6178/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
index e429baf13d..a3c8898d15 100644
--- a/src/mainboard/msi/ms7135/Config.lb
+++ b/src/mainboard/msi/ms7135/Config.lb
@@ -22,52 +22,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of the coreboot bootloader.
-##
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot ROM.
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can be cached to speed up coreboot
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte)
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE = (64 * 1024)
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
index 0b6fbc3392..3c2c83b268 100644
--- a/src/mainboard/msi/ms7260/Config.lb
+++ b/src/mainboard/msi/ms7260/Config.lb
@@ -18,33 +18,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/msi/ms9185/Config.lb b/src/mainboard/msi/ms9185/Config.lb
index 27d2ea5eb5..320feda007 100644
--- a/src/mainboard/msi/ms9185/Config.lb
+++ b/src/mainboard/msi/ms9185/Config.lb
@@ -22,39 +22,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/msi/ms9282/Config.lb b/src/mainboard/msi/ms9282/Config.lb
index 1ecfee7d28..0662bbaf56 100644
--- a/src/mainboard/msi/ms9282/Config.lb
+++ b/src/mainboard/msi/ms9282/Config.lb
@@ -22,40 +22,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/nec/powermate2000/Config.lb b/src/mainboard/nec/powermate2000/Config.lb
index 6b9d38eab4..facf500b26 100644
--- a/src/mainboard/nec/powermate2000/Config.lb
+++ b/src/mainboard/nec/powermate2000/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb
index 9031fb06df..89243cc820 100644
--- a/src/mainboard/newisys/khepri/Config.lb
+++ b/src/mainboard/newisys/khepri/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
index fcacc049dc..4513a67bca 100644
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Config.lb
@@ -19,53 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/olpc/btest/Config.lb b/src/mainboard/olpc/btest/Config.lb
index f4c24cc522..0de001a2e6 100644
--- a/src/mainboard/olpc/btest/Config.lb
+++ b/src/mainboard/olpc/btest/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index f4c24cc522..0de001a2e6 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb
index 89cb42ad79..ca4642bb40 100644
--- a/src/mainboard/pcengines/alix1c/Config.lb
+++ b/src/mainboard/pcengines/alix1c/Config.lb
@@ -18,39 +18,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/rca/rm4100/Config.lb b/src/mainboard/rca/rm4100/Config.lb
index a1eb016ad0..813021311a 100644
--- a/src/mainboard/rca/rm4100/Config.lb
+++ b/src/mainboard/rca/rm4100/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/sunw/ultra40/Config.lb b/src/mainboard/sunw/ultra40/Config.lb
index b7c20249f2..98b37191b9 100644
--- a/src/mainboard/sunw/ultra40/Config.lb
+++ b/src/mainboard/sunw/ultra40/Config.lb
@@ -1,37 +1,5 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb
index 4ed5174c8a..533e94fffd 100644
--- a/src/mainboard/supermicro/h8dme/Config.lb
+++ b/src/mainboard/supermicro/h8dme/Config.lb
@@ -16,53 +16,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
index 251175f86f..bf77981b15 100644
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ b/src/mainboard/supermicro/h8dmr/Config.lb
@@ -19,53 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/technexion/tim8690/Config.lb b/src/mainboard/technexion/tim8690/Config.lb
index 736c3c33e7..dacdb2a7dc 100644
--- a/src/mainboard/technexion/tim8690/Config.lb
+++ b/src/mainboard/technexion/tim8690/Config.lb
@@ -19,40 +19,7 @@
##
##
-
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/televideo/tc7020/Config.lb b/src/mainboard/televideo/tc7020/Config.lb
index 768aeb1722..ca91f7df71 100644
--- a/src/mainboard/televideo/tc7020/Config.lb
+++ b/src/mainboard/televideo/tc7020/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb
index 52e6e1af3d..14215bd7cd 100644
--- a/src/mainboard/thomson/ip1000/Config.lb
+++ b/src/mainboard/thomson/ip1000/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb
index bc7254a06f..dbb1258547 100644
--- a/src/mainboard/tyan/s1846/Config.lb
+++ b/src/mainboard/tyan/s1846/Config.lb
@@ -18,19 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
- + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index 4610937603..6ce8766065 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -1,37 +1,5 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
index 0a638eed58..b6b72f0b76 100644
--- a/src/mainboard/tyan/s2850/Config.lb
+++ b/src/mainboard/tyan/s2850/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2875/Config.lb b/src/mainboard/tyan/s2875/Config.lb
index f98ef57bdf..de7ecfb28c 100644
--- a/src/mainboard/tyan/s2875/Config.lb
+++ b/src/mainboard/tyan/s2875/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
index c51166f40c..87d4224e86 100644
--- a/src/mainboard/tyan/s2880/Config.lb
+++ b/src/mainboard/tyan/s2880/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb
index 09a52a0fbb..ba9853aa10 100644
--- a/src/mainboard/tyan/s2881/Config.lb
+++ b/src/mainboard/tyan/s2881/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
index de20881e8a..2acaae12b5 100644
--- a/src/mainboard/tyan/s2882/Config.lb
+++ b/src/mainboard/tyan/s2882/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 94df0a4845..ced1583246 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index d54a5b2a9b..944b95d1fe 100644
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -1,41 +1,8 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+include /config/nofailovercalculation.lb
default CONFIG_ROM_PAYLOAD = 1
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
arch i386 end
-
##
## Build the objects we have code for in this directory.
##
diff --git a/src/mainboard/tyan/s2892/Config.lb b/src/mainboard/tyan/s2892/Config.lb
index 077d769cef..f8d7cafdda 100644
--- a/src/mainboard/tyan/s2892/Config.lb
+++ b/src/mainboard/tyan/s2892/Config.lb
@@ -1,37 +1,5 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index ab081a8816..eb5964f0d9 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -1,50 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
index 902ae846d0..b2a23b5c0c 100644
--- a/src/mainboard/tyan/s2912/Config.lb
+++ b/src/mainboard/tyan/s2912/Config.lb
@@ -19,53 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
index cb9e9a017c..b2e6eb2f19 100644
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ b/src/mainboard/tyan/s2912_fam10/Config.lb
@@ -19,53 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+include /config/failovercalculation.lb
arch i386 end
diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb
index 052e5fa565..9cc755841d 100644
--- a/src/mainboard/tyan/s4880/Config.lb
+++ b/src/mainboard/tyan/s4880/Config.lb
@@ -1,37 +1,5 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
index ad8c06b385..853b1606de 100644
--- a/src/mainboard/tyan/s4882/Config.lb
+++ b/src/mainboard/tyan/s4882/Config.lb
@@ -1,37 +1,5 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
+default CONFIG_ROM_PAYLOAD = 1
arch i386 end
diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb
index 7f1e59abc3..649a784961 100644
--- a/src/mainboard/via/epia-cn/Config.lb
+++ b/src/mainboard/via/epia-cn/Config.lb
@@ -19,18 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
index 2ebd2096cc..2848c474ea 100644
--- a/src/mainboard/via/epia-m/Config.lb
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index 0ccd060a89..59362238da 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
diff --git a/src/mainboard/via/pc2500e/Config.lb b/src/mainboard/via/pc2500e/Config.lb
index b6aca0506f..f18e829b39 100644
--- a/src/mainboard/via/pc2500e/Config.lb
+++ b/src/mainboard/via/pc2500e/Config.lb
@@ -18,18 +18,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
-else
- default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- default ROM_SECTION_OFFSET = 0
-end
-default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
-default XIP_ROM_SIZE = 64 * 1024
-default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+include /config/nofailovercalculation.lb
+
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb
index 5cda9d228e..ca98463417 100644
--- a/src/mainboard/via/vt8454c/Config.lb
+++ b/src/mainboard/via/vt8454c/Config.lb
@@ -19,39 +19,7 @@
## MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture