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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-09-30 10:27:01 +0530
committerKarthik Ramasubramanian <kramasub@google.com>2020-10-08 19:43:56 +0000
commitb5e4e3441841d8d1b7fac1240b7c73d288df66d5 (patch)
tree9d03c495a66e83f54f45797f154323d68d86991c
parent833b5b33d2fe330873c2412193113bc4ff3fc5f3 (diff)
downloadcoreboot-b5e4e3441841d8d1b7fac1240b7c73d288df66d5.tar.xz
mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperature
Update TSR1 passive trip temperature BUG=b:169691800 BRANCH=None TEST=Built and tested on dedede system Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
-rw-r--r--src/mainboard/google/dedede/variants/drawcia/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
index fa10152a4e..715da7aaa2 100644
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -75,7 +75,7 @@ chip soc/intel/jasperlake
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 1000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000)"
- register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 1000)"
+ register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000)"
register "policies.passive[3]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000)"
register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000)"