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authorDave Frodin <dave.frodin@se-eng.com>2015-05-01 09:17:43 -0600
committerDave Frodin <dave.frodin@se-eng.com>2015-05-01 17:29:00 +0200
commitb738913ce050cd5a61d902e7024d4881cdb1ae59 (patch)
tree6130a5facd89a094857e6fdcce894184150e6a4d
parent2eaa0d49e10e9c2314b0f61400a481447d1df892 (diff)
downloadcoreboot-b738913ce050cd5a61d902e7024d4881cdb1ae59.tar.xz
northbridge/intel/fsp_rangeley: Correct MMIO size setting
The Rangeley chipset has the MMIO PCI config space feature enabled at 0xe0000000-0xefffffff. This is a 256MB space which covers all of config space. The ACPI table for this space only defines it as being 64MB. This change fixes that setting. Change-Id: I8205a9b89ea6633ac6c4b0d5a282cd2745595b2e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10047 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
index 6a8c2e07a7..08dba89a71 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000)
+ Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
})
// Current Resource Settings