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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-08-05 08:23:52 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-08-06 12:04:01 +0000 |
| commit | c4d56d668f682f7d0d77a2e02f4728b1299f406e (patch) | |
| tree | 32a001bc825b8eee401f3e82996739d08101b719 | |
| parent | be207b10988cd81b0f8da16cac958e8456987a69 (diff) | |
| download | coreboot-c4d56d668f682f7d0d77a2e02f4728b1299f406e.tar.xz | |
Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
| -rw-r--r-- | Documentation/arch/riscv/index.md | 17 | ||||
| -rw-r--r-- | Documentation/mainboard/sifive/hifive-unleashed.md | 1 |
2 files changed, 16 insertions, 2 deletions
diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index 9a5de34f09..ea6a5cd47e 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -23,8 +23,20 @@ On entry to a stage or payload (including SELF payloads), ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT. +## OpenSBI +In case the payload doesn't install it's own SBI, like the [RISCV-PK] does, +[OpenSBI] can be used instead. +It's loaded into RAM after coreboot has finished loading the payload. +coreboot then will jump to OpenSBI providing a pointer to the real payload, +which OpenSBI will jump to once the SBI is installed. + +Besides providing SBI it also sets protected memory regions and provides +a platform independent console. + +The OpenSBI code is always run in M mode. + ## Trap delegation -Traps are delegated in the ramstage. +Traps are delegated to the payload. ## SMP within a stage At the beginning of each stage, all harts save 0 are spinning in a loop on @@ -44,3 +56,6 @@ The hart blocks until fn is non-null, and then calls it. If fn returns, we will panic if possible, but behavior is largely undefined. Only hart 0 runs through most of the code in each stage. + +[RISCV-PK]: https://github.com/riscv/riscv-pk +[OpenSBI]: https://github.com/riscv/opensbi diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 495dade212..4dbbf0e073 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -17,7 +17,6 @@ The following things are still missing from this coreboot port: - Provide serial number to payload (e.g. in device tree) - Implement instruction emulation - Support for booting Linux on RISC-V -- Add support to run OpenSBI payload in m-mode - SMP support in trap handler ## Configuration |