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authorWonkyu Kim <wonkyu.kim@intel.com>2020-05-27 13:34:04 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-17 09:18:45 +0000
commitc66c15334adb100eb55253cb03dbc4605becee46 (patch)
treef9c9297ef95e762c1110e38b6f304200b89ae13c
parent549a853f8f50cb99098f7abec6e93efe7224ee82 (diff)
downloadcoreboot-c66c15334adb100eb55253cb03dbc4605becee46.tar.xz
soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD
This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/chip.h1
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 9c179693ed..30377aaf79 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -135,6 +135,7 @@ struct soc_intel_tigerlake_config {
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index b9dbec87f5..3fbb89a793 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -165,6 +165,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
+ params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
}
/* Enable ClkReqDetect for enabled port */