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authorRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
commitc994c973c654817f5e764615776b78b84cd21910 (patch)
tree37e35c7cd905ef9b5cacc8dbd76628c134e5f68c
parentd96e098def3ed64be0b775d4a6c058821e33b5ef (diff)
downloadcoreboot-c994c973c654817f5e764615776b78b84cd21910.tar.xz
Fix for nehemiah
other fixes for gx2 ram init. support for sharplfg00l04 -- not working yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/amd/rumba/auto.c18
-rw-r--r--src/mainboard/lippert/frontrunner/auto.c27
-rw-r--r--src/mainboard/via/epia-m/mainboard.c5
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c9
-rw-r--r--src/northbridge/amd/gx2/raminit.c17
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c5
-rw-r--r--util/flashrom/flashchips.c2
-rw-r--r--util/flashrom/sharplhf00l04.c214
-rw-r--r--util/flashrom/sharplhf00l04.h39
9 files changed, 231 insertions, 105 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 72d1ef4e0e..19f7049c8e 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -19,6 +19,24 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
+ msr_t msr;
+ /* 1. Initialize GLMC registers base on SPD values,
+ * Hard coded as XpressROM for now */
+ //print_debug("sdram_enable step 1\r\n");
+ msr = rdmsr(0x20000018);
+ msr.hi = 0x10076013;
+ msr.lo = 0x00003000;
+ wrmsr(0x20000018, msr);
+
+ msr = rdmsr(0x20000019);
+ msr.hi = 0x18000108;
+ msr.lo = 0x696332a3;
+ wrmsr(0x20000019, msr);
+
+
+}
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
diff --git a/src/mainboard/lippert/frontrunner/auto.c b/src/mainboard/lippert/frontrunner/auto.c
index 72d1ef4e0e..5ad5576291 100644
--- a/src/mainboard/lippert/frontrunner/auto.c
+++ b/src/mainboard/lippert/frontrunner/auto.c
@@ -19,11 +19,32 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
+
+/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ msr_t msr;
+ /* 1. Initialize GLMC registers base on SPD values,
+ * Hard coded as XpressROM for now */
+ //print_debug("sdram_enable step 1\r\n");
+ msr = rdmsr(0x20000018);
+ msr.hi = 0x10076013;
+ msr.lo = 0x3400;
+ wrmsr(0x20000018, msr);
+
+ msr = rdmsr(0x20000019);
+ msr.hi = 0x18000008;
+ msr.lo = 0x696332a3;
+ wrmsr(0x20000019, msr);
+
+}
+
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/gx2/pll_reset.c"
+
static void msr_init(void)
{
__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
@@ -63,15 +84,15 @@ static void main(unsigned long bist)
console_init();
cs5535_early_setup();
-
+ print_err("done cs5535 early\n");
pll_reset();
-
+ print_err("done pll_reset\n");
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
sdram_initialize(1, memctrl);
-
+ print_err("Done sdram_initialize\n");
/* Check all of memory */
ram_check(0x00000000, 640*1024);
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index 26e5916f01..da27732d63 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -30,6 +30,11 @@ void write_protect_vgabios(void)
device_t dev;
printk_info("write_protect_vgabios\n");
+ /* there are two possible devices. Just do both. */
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
+ if(dev)
+ pci_write_config8(dev, 0x61, 0xaa);
+
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
if(dev)
pci_write_config8(dev, 0x61, 0xaa);
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index b84e62e8b2..0e3a3caf95 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -122,9 +122,14 @@ static void pll_reset(void)
/* get CPU core clock in MHZ */
cpu_core = calibrate_tsc();
- get_memory_speed();
+ print_debug("Cpu core is ");
+ print_debug_hex32(cpu_core);
+ print_debug("\n");
+ //get_memory_speed();
//msr = rdmsr(GLCP_SYS_RSTPLL);
msr = rdmsr(0x4c000014);
+ print_debug("4c000014 is ");
+ print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); print_debug("\n");
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
print_debug("disable PLL bypass\n\r");
@@ -162,7 +167,7 @@ static void pll_reset(void)
print_debug("\n\r");
//gliu = get_memory_speed();
- get_memory_speed();
+ //get_memory_speed();
//print_debug("Target Memory Clock ");
//print_debug_hex32(gliu);
//print_debug("\n\r");
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 95ce72a10e..a2cc474a3a 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -4,10 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
-
-}
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
@@ -16,19 +12,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
int i;
msr_t msr;
- /* 1. Initialize GLMC registers base on SPD values,
- * Hard coded as XpressROM for now */
- //print_debug("sdram_enable step 1\r\n");
- msr = rdmsr(0x20000018);
- msr.hi = 0x10076013;
- msr.lo = 0x00003000;
- wrmsr(0x20000018, msr);
-
- msr = rdmsr(0x20000019);
- msr.hi = 0x18000108;
- msr.lo = 0x696332a3;
- wrmsr(0x20000019, msr);
-
/* 2. clock gating for PMode */
msr = rdmsr(0x20002004);
msr.lo &= ~0x04;
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index ae3b7df441..6c32498aa9 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -103,10 +103,15 @@ static int cs5535_early_setup(void)
print_debug("reboot from BIOS reset\n\r");
return;
}
+ print_debug("Setup idsel\r\n");
cs5535_setup_idsel();
+ print_debug("Setup iobase\r\n");
cs5535_setup_iobase();
+ print_debug("Setup gpio\r\n");
cs5535_setup_gpio();
+ print_debug("Setup cis_mode\r\n");
cs5535_setup_cis_mode();
+ print_debug("Setup smbus\r\n");
cs5535_enable_smbus();
//get_memory_speed();
dummy();
diff --git a/util/flashrom/flashchips.c b/util/flashrom/flashchips.c
index 08eb00cdd1..f718e7b140 100644
--- a/util/flashrom/flashchips.c
+++ b/util/flashrom/flashchips.c
@@ -89,7 +89,7 @@ struct flashchip flashchips[] = {
probe_md2802, erase_md2802, write_md2802, read_md2802},
#endif
{"LHF00L04", SHARP_ID, SHARP_LHF00L04, NULL, 1024, 64 * 1024,
- probe_82802ab, erase_82802ab, write_82802ab, NULL},
+ probe_lhf00l04, erase_lhf00l04, write_lhf00l04, NULL},
{NULL,}
};
diff --git a/util/flashrom/sharplhf00l04.c b/util/flashrom/sharplhf00l04.c
index e7e5eedfea..5b485ada8e 100644
--- a/util/flashrom/sharplhf00l04.c
+++ b/util/flashrom/sharplhf00l04.c
@@ -1,9 +1,8 @@
/*
- * sst28sf040.c: driver for SST28SF040C flash models.
+ * lhf00l04.c: driver for programming JEDEC standard flash parts
*
*
* Copyright 2000 Silicon Integrated System Corporation
- * Copyright 2005 coresystems GmbH <stepan@openbios.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,111 +19,164 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
- * Reference:
- * 8 MEgabit (1024K x 8) SHARP LHF00L04, data sheet
+ * Reference: http://www.intel.com/design/chipsets/datashts/290658.htm
*
+ * $Id: lhf00l04.c 2111 2005-11-26 21:55:36Z ollie $
*/
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/io.h>
+#include <unistd.h>
#include <stdio.h>
-#include <stdint.h>
+#include <stdlib.h>
+
#include "flash.h"
+#include "sharplhf00l04.h"
#include "debug.h"
-
-#define AUTO_PG_ERASE1 0x20
-#define AUTO_PG_ERASE2 0xD0
-#define AUTO_PGRM 0x10
-#define CHIP_ERASE 0x30
-#define RESET 0xFF
-#define READ_ID 0x90
-
-static __inline__ void protect_lhf00l04(volatile uint8_t *bios)
+// I need that Berkeley bit-map printer
+void print_lhf00l04_status(uint8_t status)
{
- /* ask compiler not to optimize this */
-// volatile uint8_t tmp;
-
+ printf("%s", status & 0x80 ? "Ready:" : "Busy:");
+ printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
+ printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
+ printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
+ printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
+ printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
+ printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
}
-static __inline__ void unprotect_lhf00l04(volatile uint8_t *bios)
+int probe_lhf00l04(struct flashchip *flash)
{
- /* ask compiler not to optimize this */
-// volatile uint8_t tmp;
-}
+ volatile uint8_t *bios = flash->virt_addr;
+ uint8_t id1, id2;
-static __inline__ int erase_sector_lhf00l04(volatile uint8_t *bios,
- unsigned long address)
-{
+#if 0
+ *(volatile uint8_t *) (bios + 0x5555) = 0xAA;
+ *(volatile uint8_t *) (bios + 0x2AAA) = 0x55;
+ *(volatile uint8_t *) (bios + 0x5555) = 0x90;
+#endif
- return (0);
-}
+ *bios = 0xff;
+ myusec_delay(10);
+ *bios = 0x90;
+ myusec_delay(10);
-static __inline__ int write_sector_lhf00l04(volatile uint8_t *bios,
- uint8_t *src,
- volatile uint8_t *dst,
- unsigned int page_size)
-{
- int i;
+ id1 = *(volatile uint8_t *) bios;
+ id2 = *(volatile uint8_t *) (bios + 0x01);
- for (i = 0; i < page_size; i++) {
- /* transfer data from source to destination */
- if (*src == 0xFF) {
- dst++, src++;
- /* If the data is 0xFF, don't program it */
- continue;
+#if 1
+ *(volatile uint8_t *) (bios + 0x5555) = 0xAA;
+ *(volatile uint8_t *) (bios + 0x2AAA) = 0x55;
+ *(volatile uint8_t *) (bios + 0x5555) = 0xF0;
+
+#endif
+ myusec_delay(10);
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id) {
+ size_t size = flash->total_size * 1024;
+ // we need to mmap the write-protect space.
+ bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
+ flash->fd_mem, (off_t) (0 - 0x400000 - size));
+ if (bios == MAP_FAILED) {
+ // it's this part but we can't map it ...
+ perror("Error MMAP /dev/mem");
+ exit(1);
}
- /*issue AUTO PROGRAM command */
- *dst = AUTO_PGRM;
- *dst++ = *src++;
- /* wait for Toggle bit ready */
-// toggle_ready_jedec(bios);
+ flash->virt_addr_2 = bios;
+ printf("bios %p, *bios 0x%x, bios[1] 0x%x\n", bios, *bios, bios[1]);
+ return 1;
}
- return (0);
+ return 0;
}
-int probe_lhf00l04(struct flashchip *flash)
+uint8_t wait_lhf00l04(volatile uint8_t *bios)
{
- volatile uint8_t *bios = flash->virt_addr;
- uint8_t id1, id2, tmp;
- /* save the value at the beginning of the Flash */
- tmp = *bios;
+ uint8_t status;
+ uint8_t id1, id2;
- *bios = RESET;
- myusec_delay(10);
+ *bios = 0x70;
+ if ((*bios & 0x80) == 0) { // it's busy
+ while ((*bios & 0x80) == 0);
+ }
+
+ status = *bios;
- *bios = READ_ID;
+ // put another command to get out of status register mode
+
+ *bios = 0x90;
myusec_delay(10);
+
id1 = *(volatile uint8_t *) bios;
- myusec_delay(10);
id2 = *(volatile uint8_t *) (bios + 0x01);
- *bios = RESET;
- myusec_delay(10);
-
- printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
- if (id1 == flash->manufacture_id && id2 == flash->model_id)
- return 1;
+ // this is needed to jam it out of "read id" mode
+ *(volatile uint8_t *) (bios + 0x5555) = 0xAA;
+ *(volatile uint8_t *) (bios + 0x2AAA) = 0x55;
+ *(volatile uint8_t *) (bios + 0x5555) = 0xF0;
+ return status;
- /* if there is no lhf00l04, restore the original value */
- *bios = tmp;
- return 0;
}
-
+int erase_lhf00l04_block(struct flashchip *flash, int offset)
+{
+ volatile uint8_t *bios = flash->virt_addr + offset;
+ volatile uint8_t *wrprotect =
+ flash->virt_addr_2 + offset + 2;
+ uint8_t status;
+
+ // clear status register
+ *bios = 0x50;
+ printf("Erase at %p\n", bios);
+ status = wait_lhf00l04(flash->virt_addr);
+ print_lhf00l04_status(status);
+ // clear write protect
+ printf("write protect is at %p\n", (wrprotect));
+ printf("write protect is 0x%x\n", *(wrprotect));
+ *(wrprotect) = 0;
+ printf("write protect is 0x%x\n", *(wrprotect));
+
+ // now start it
+ *(volatile uint8_t *) (bios) = 0x20;
+ *(volatile uint8_t *) (bios) = 0xd0;
+ myusec_delay(10);
+ // now let's see what the register is
+ status = wait_lhf00l04(flash->virt_addr);
+ print_lhf00l04_status(status);
+ printf("DONE BLOCK 0x%x\n", offset);
+ return (0);
+}
int erase_lhf00l04(struct flashchip *flash)
{
- volatile uint8_t *bios = flash->virt_addr;
+ int i;
+ unsigned int total_size = flash->total_size * 1024;
- unprotect_lhf00l04(bios);
- *bios = CHIP_ERASE;
- *bios = CHIP_ERASE;
- protect_lhf00l04(bios);
+ printf("total_size is %d; flash->page_size is %d\n",
+ total_size, flash->page_size);
+ for (i = 0; i < total_size; i += flash->page_size)
+ erase_lhf00l04_block(flash, i);
+ printf("DONE ERASE\n");
+ return (0);
+}
- myusec_delay(10);
-// toggle_ready_jedec(bios);
+void write_page_lhf00l04(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst,
+ int page_size)
+{
+ int i;
+
+ for (i = 0; i < page_size; i++) {
+ /* transfer data from source to destination */
+ *dst = 0x40;
+ *dst++ = *src++;
+ wait_lhf00l04(bios);
+ }
- return (0);
}
int write_lhf00l04(struct flashchip *flash, uint8_t *buf)
@@ -134,22 +186,20 @@ int write_lhf00l04(struct flashchip *flash, uint8_t *buf)
flash->page_size;
volatile uint8_t *bios = flash->virt_addr;
- unprotect_lhf00l04(bios);
-
+ erase_lhf00l04(flash);
+ if (*bios != 0xff) {
+ printf("ERASE FAILED\n");
+ return -1;
+ }
printf("Programming Page: ");
for (i = 0; i < total_size / page_size; i++) {
- /* erase the page before programming */
- erase_sector_lhf00l04(bios, i * page_size);
-
- /* write to the sector */
printf("%04d at address: 0x%08x", i, i * page_size);
- write_sector_lhf00l04(bios, buf + i * page_size,
- bios + i * page_size, page_size);
- printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
+ write_page_lhf00l04(bios, buf + i * page_size,
+ bios + i * page_size, page_size);
+ printf
+ ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
}
printf("\n");
-
protect_lhf00l04(bios);
-
return (0);
}
diff --git a/util/flashrom/sharplhf00l04.h b/util/flashrom/sharplhf00l04.h
index d615dfa44b..3b8852a828 100644
--- a/util/flashrom/sharplhf00l04.h
+++ b/util/flashrom/sharplhf00l04.h
@@ -4,5 +4,44 @@
extern int probe_lhf00l04(struct flashchip *flash);
extern int erase_lhf00l04(struct flashchip *flash);
extern int write_lhf00l04(struct flashchip *flash, uint8_t *buf);
+extern __inline__ void toggle_ready_lhf00l04(volatile uint8_t *dst)
+{
+ unsigned int i = 0;
+ uint8_t tmp1, tmp2;
+
+ tmp1 = *dst & 0x40;
+
+ while (i++ < 0xFFFFFF) {
+ tmp2 = *dst & 0x40;
+ if (tmp1 == tmp2) {
+ break;
+ }
+ tmp1 = tmp2;
+ }
+}
+
+extern __inline__ void data_polling_lhf00l04(volatile uint8_t *dst, uint8_t data)
+{
+ unsigned int i = 0;
+ uint8_t tmp;
+
+ data &= 0x80;
+
+ while (i++ < 0xFFFFFF) {
+ tmp = *dst & 0x80;
+ if (tmp == data) {
+ break;
+ }
+ }
+}
+
+extern __inline__ void protect_lhf00l04(volatile uint8_t *bios)
+{
+ *(volatile uint8_t *) (bios + 0x5555) = 0xAA;
+ *(volatile uint8_t *) (bios + 0x2AAA) = 0x55;
+ *(volatile uint8_t *) (bios + 0x5555) = 0xA0;
+
+ usleep(200);
+}
#endif /* !__SHARPLHF00L04_H__ */