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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-09 12:40:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-10 15:15:14 +0000 |
| commit | c9f6bd90857d3a7efe08c60f7f5fc19995fb1756 (patch) | |
| tree | e4db63a2081fe2f4d87cd35223c597a27cab4e60 | |
| parent | 9d9ce62ae9bd122e43ab87468de541a822a0ff1f (diff) | |
| download | coreboot-c9f6bd90857d3a7efe08c60f7f5fc19995fb1756.tar.xz | |
sb/i82801gx: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).
BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx
(see ICH7 Family Datasheet page 355).
The write on that register is already done some lines above.
So remove wrong register name and the wrong code line.
Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/southbridge/intel/i82801gx/pci.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769fff3..22c516581f 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; |