diff options
author | Angel Pons <th3fanbus@gmail.com> | 2021-01-22 15:17:19 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 08:50:34 +0000 |
commit | cbde6410a039b37d0df07e53953baad552bd22cc (patch) | |
tree | 5b49d81e482d2f0111f2bc299968263423d75d29 | |
parent | e4abe7fd5afcf35db8ac51969f716592f4bdf253 (diff) | |
download | coreboot-cbde6410a039b37d0df07e53953baad552bd22cc.tar.xz |
mb/google/kahlee: Deduplicate now-equivalent mainboard.c
The only difference is an additional include that is no longer needed.
Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
9 files changed, 1 insertions, 210 deletions
diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc index 24e0090c5e..3a8e8607ad 100644 --- a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index 9f33a0b224..a41ba22e8b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += memory.c romstage-y += tpm_tis.c ramstage-y += gpio.c +ramstage-y += mainboard.c ramstage-y += tpm_tis.c # Add OEM ID table diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index cd19d7cab5..e50e6b9db5 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -4,5 +4,3 @@ subdirs-y += ./spd bootblock-y += variant.c romstage-y += variant.c - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index 24e0090c5e..3a8e8607ad 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index 24e0090c5e..3a8e8607ad 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc index c4dcffc780..21b0276a72 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd - -ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c deleted file mode 100644 index afb62ba5dd..0000000000 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <ec/google/chromeec/ec.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <cbfs.h> -#include <gpio.h> -#include <smbios.h> -#include <variant/gpio.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/generic/bayhub/bh720.h> - -uint32_t sku_id(void) -{ - static int sku = -1; - - if (sku == -1) - sku = google_chromeec_get_sku_id(); - - return sku; -} - -uint8_t variant_board_sku(void) -{ - return sku_id(); -} - -void variant_mainboard_suspend_resume(void) -{ - /* Enable backlight - GPIO 133 active low */ - gpio_set(GPIO_133, 0); -} - -void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); -} - -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_bin_data[11]; - static const char *manuf; - - if (!CONFIG(USE_OEM_BIN)) - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - if (manuf) - return manuf; - - if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) - manuf = &oem_bin_data[0]; - else - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - return manuf; -} diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index c4dcffc780..21b0276a72 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd - -ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c deleted file mode 100644 index afb62ba5dd..0000000000 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <ec/google/chromeec/ec.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <cbfs.h> -#include <gpio.h> -#include <smbios.h> -#include <variant/gpio.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <drivers/generic/bayhub/bh720.h> - -uint32_t sku_id(void) -{ - static int sku = -1; - - if (sku == -1) - sku = google_chromeec_get_sku_id(); - - return sku; -} - -uint8_t variant_board_sku(void) -{ - return sku_id(); -} - -void variant_mainboard_suspend_resume(void) -{ - /* Enable backlight - GPIO 133 active low */ - gpio_set(GPIO_133, 0); -} - -void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); -} - -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_bin_data[11]; - static const char *manuf; - - if (!CONFIG(USE_OEM_BIN)) - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - if (manuf) - return manuf; - - if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) - manuf = &oem_bin_data[0]; - else - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - return manuf; -} |