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authorwxjstz <wxjstz@126.com>2017-06-06 16:50:46 +0800
committerMartin Roth <martinroth@google.com>2017-09-26 16:50:36 +0000
commitd277960eb8f7c8ed068f1823049c701e00ea8e46 (patch)
tree28a5998c5749e9c40f59d66ab31761be0067f6ef
parenta57cc2ffb2244c6c93b2e33de4168f12fc8faf29 (diff)
downloadcoreboot-d277960eb8f7c8ed068f1823049c701e00ea8e46.tar.xz
riscv: Update register address
I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception[csrwi 0x320,7]. This is operate for mcounteren. This address is error. 0x306 is right. scounteren is not need to be set, because S-mode code controls it. Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Signed-off-by: wxjstz<wxjstz@126.com> Reviewed-on: https://review.coreboot.org/20043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
-rw-r--r--src/arch/riscv/virtual_memory.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2c440d24aa..1fff1d170a 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -311,11 +311,10 @@ void mstatus_init(void)
set_csr(medeleg, delegate);
// Enable all user/supervisor-mode counters using
- // v1.9.1 register addresses.
+ // v1.10 register addresses.
// They moved from the earlier spec.
// Until we trust our toolchain use the hardcoded constants.
// These were in flux and people who get the older toolchain
// will have difficult-to-debug failures.
- write_csr(/*mucounteren*/0x320, 7);
- write_csr(/*mscounteren*/0x321, 7);
+ write_csr(/*mcounteren*/0x306, 7);
}