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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-16 19:28:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-16 20:40:47 +0100 |
| commit | d4d5e4d3e10da06a83d57a147bd58a733381de18 (patch) | |
| tree | 521b13c4eb4b983f6717f9fb05cb08d7f8d177dc | |
| parent | 35e1c861f59696e2ff545e89709e5e72ccc79fca (diff) | |
| download | coreboot-d4d5e4d3e10da06a83d57a147bd58a733381de18.tar.xz | |
Via Epia-N and C3: Set ioapic delivery type in Kconfig
The original comment says it's a Via C3 and not Epia requirement
to deliver IOAPIC interrupts on APIC serial bus.
Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/435
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/arch/x86/Kconfig | 8 | ||||
| -rw-r--r-- | src/arch/x86/lib/ioapic.c | 12 | ||||
| -rw-r--r-- | src/cpu/via/c3/Kconfig | 1 |
3 files changed, 11 insertions, 10 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f313a..c5a0c0e2f5 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -88,4 +88,12 @@ config LITTLE_ENDIAN bool default !BIG_ENDIAN +config IOAPIC_INTERRUPTS_ON_FSB + bool + default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + +config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + bool + default n + endmenu diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 81d964cf94..e974d7cce6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. -#if CONFIG_EPIA_VT8237R_INIT -#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -#else -#define IOAPIC_INTERRUPTS_ON_FSB -#endif - -#ifdef IOAPIC_INTERRUPTS_ON_FSB +#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif -#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig index a5b4f22673..259a1f211d 100644 --- a/src/cpu/via/c3/Kconfig +++ b/src/cpu/via/c3/Kconfig @@ -7,5 +7,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select UDELAY_TSC select MMX + select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS endif # CPU_VIA_C3 |