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authorSubrata Banik <subrata.banik@intel.com>2018-01-18 15:13:53 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-01-24 13:26:28 +0000
commitd99f9d526f9e46442b1d0158d7f881202b293183 (patch)
treeb887b25cb6aa2d0427025044f48844962e23941c
parentb7d79cddf0287a2e925d2003ef8d0cde6bbbae2a (diff)
downloadcoreboot-d99f9d526f9e46442b1d0158d7f881202b293183.tar.xz
soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference code
Solution: To do an additional config read to the eMMC controller after the controller has been power gated (put to D3) Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl20
1 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index e993ddbbf9..a9fd35e1b9 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,21 +17,33 @@ Scope (\_SB.PCI0) {
/* EMMC */
Device(PEMC) {
Name(_ADR, 0x001A0000)
+ Name (TEMP, 0)
OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
Field(SCSR, WordAcc, NoLock, Preserve) {
- Offset(0xA2), // 0xA2, Device PG config
+ Offset (0x84), /* PMECTRLSTATUS */
+ PMCR, 16,
+ Offset (0xA2), /* PG_CONFIG */
, 2,
- PGEN, 1 // [BIT2] PGE - PG Enable
+ PGEN, 1, /* PG_ENABLE */
}
Method(_PS0, 0, Serialized) {
- Stall (50) // Sleep 50 ms
+ Stall (50) // Sleep 50 us
+
Store(0, PGEN) // Disable PG
+
+ /* Set Power State to D0 */
+ And (PMCR, 0xFFFC, PMCR)
+ Store (PMCR, ^TEMP)
}
Method(_PS3, 0, Serialized) {
Store(1, PGEN) // Enable PG
+
+ /* Set Power State to D3 */
+ Or (PMCR, 0x0003, PMCR)
+ Store (PMCR, ^TEMP)
}
}