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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 19:04:55 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 10:16:41 +0000
commitdad7f37f729cee52c8839e18803042e5cf2309c7 (patch)
treef6ccb99f3d7db48d757ead52f65f75a4f7aeb064
parente1484e4b3e4ae26539732fe87712357811e6ba06 (diff)
downloadcoreboot-dad7f37f729cee52c8839e18803042e5cf2309c7.tar.xz
mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fields
They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/mainboard/asus/p8h61-m_pro/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
index e791d70976..166a625a82 100644
--- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb
+++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
@@ -32,9 +32,7 @@ chip northbridge/intel/sandybridge
device domain 0x0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
- register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291" # HWM
- register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"