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authorFurquan Shaikh <furquan@google.com>2014-07-25 14:52:57 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-23 13:15:49 +0100
commitdbf3670977a7e02cdc52a8dd15effdf4006b08df (patch)
tree672b307690501f34ae55a30645e1d895f71fe46c
parente4a642c86713e98617173477b9327cfd3c4cd369 (diff)
downloadcoreboot-dbf3670977a7e02cdc52a8dd15effdf4006b08df.tar.xz
t132: Add support for tpm i2c
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/rush/romstage.c32
-rw-r--r--src/mainboard/google/rush_ryu/romstage.c4
-rw-r--r--src/soc/nvidia/tegra132/include/soc/romstage.h1
-rw-r--r--src/soc/nvidia/tegra132/romstage.c3
4 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index bb173c09d6..7c01a30604 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -19,6 +19,38 @@
#include <soc/romstage.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void configure_tpm_i2c_bus(void)
+{
+ clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
+
+ i2c_init(2);
+}
+
+void mainboard_init_tpm_i2c(void)
+{
+ clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
+
+ gpio_output(GPIO(I5), 1);
+
+ // I2C3 (cam) clock.
+ pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+ PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+ // I2C3 (cam) data.
+ pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+ PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+
+
+ configure_tpm_i2c_bus();
+}
+
void mainboard_configure_pmc(void)
{
}
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index bb173c09d6..9a41247dd8 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -19,6 +19,10 @@
#include <soc/romstage.h>
+void mainboard_init_tpm_i2c(void)
+{
+}
+
void mainboard_configure_pmc(void)
{
}
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index f9eac26e0d..f66912151e 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -22,5 +22,6 @@
void mainboard_configure_pmc(void);
void mainboard_enable_vdd_cpu(void);
+void mainboard_init_tpm_i2c(void);
#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 812d14798c..69271f0088 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -30,6 +30,7 @@
#include "ccplex.h"
#include <soc/clock.h>
+#include <soc/romstage.h>
void romstage(void);
void romstage(void)
@@ -66,6 +67,8 @@ void romstage(void)
ccplex_load_mts();
printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
+ mainboard_init_tpm_i2c();
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");