summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2015-12-10 01:01:59 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-18 12:09:37 +0100
commitddd9f1a5a65db7a461ffb6576ca45acf56c2b000 (patch)
tree58c44240e03ea6ea1d4d3328d07c8dec8f741080
parent63f8c0af4ba934f0a9eaefaed6ae411404962196 (diff)
downloadcoreboot-ddd9f1a5a65db7a461ffb6576ca45acf56c2b000.tar.xz
intel/skylake: Add devicetree setting for DDR frequency limit UPD
There is a UPD setting exposed by FSP that allows the DDR frequency to be limited. Expose this for devicetree. BUG=chrome-os-partner:47346 BRANCH=none TEST=tested by limiting DDR frequency to 1600 on chell EVT Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220 Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12981 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/intel/skylake/chip.h6
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c1
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1c45470b9f..7e401ebb8e 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -113,6 +113,12 @@ struct soc_intel_skylake_config {
u32 TsegSize;
u16 MmioSize;
+ /*
+ * DDR Frequency Limit
+ * 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
+ */
+ u16 DdrFreqLimit;
+
/* Probeless Trace function */
u8 ProbelessTrace;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 5481004121..31f7fc29da 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -92,6 +92,7 @@ void soc_memory_init_params(struct romstage_params *params,
upd->EnableTraceHub = config->EnableTraceHub;
upd->SaGv = config->SaGv;
upd->RMT = config->Rmt;
+ upd->DdrFreqLimit = config->DdrFreqLimit;
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,