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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-05-17 19:50:54 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-18 17:03:43 +0000
commitdf092c1ded6eaf27ee31f75784b04a37b93f83e1 (patch)
tree7c0571c373a67f5ae8aad6b4d6e9f55fbdd6964b
parenta77eb6e6c3d6b83bd63b6ea8dd9b3e22ed985347 (diff)
downloadcoreboot-df092c1ded6eaf27ee31f75784b04a37b93f83e1.tar.xz
soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl
We were not adding power management handling of GPIO_COM3 in gpio.asl This can affect s0ix flow where platform won't go into s0ix since GPIO_COM3 is not power gated. BUG=b:188392183 BRANCH=None TEST=Platform should enter to s0ix and GPIO COMM3 should not block an entry to s0ix. Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/soc/intel/alderlake/acpi/gpio.asl11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl
index 50d999f7f4..376afaba1e 100644
--- a/src/soc/intel/alderlake/acpi/gpio.asl
+++ b/src/soc/intel/alderlake/acpi/gpio.asl
@@ -80,6 +80,12 @@ Method (GADD, 1, NotSerialized)
Local0 = PID_GPIOCOM2
Local1 = Arg0 - GPIO_COM2_START
}
+ /* GPIO Community 3 */
+ If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END)
+ {
+ Local0 = PID_GPIOCOM3
+ Local1 = Arg0 - GPIO_COM3_START
+ }
/* GPIO Community 4 */
If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
{
@@ -115,6 +121,9 @@ Method (GPID, 1, Serialized)
Case (COMM_2) {
Local0 = PID_GPIOCOM2
}
+ case (COMM_3) {
+ Local0 = PID_GPIOCOM3
+ }
Case (COMM_4) {
Local0 = PID_GPIOCOM4
}
@@ -130,7 +139,7 @@ Method (GPID, 1, Serialized)
}
/* GPIO Power Management bits */
-Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0})
/*
* Save GPIO Power Management bits