diff options
| author | Keith Hui <buurin@gmail.com> | 2020-05-05 21:52:35 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-06 07:10:13 +0000 |
| commit | e22c597bf64413ee4329c8869484d8a1f290f217 (patch) | |
| tree | cb69809b06f7682100d1d3b018c3b1fa40e6077d | |
| parent | 6462cbb2c20bae0cf309a3eb4ce70adff573e75a (diff) | |
| download | coreboot-e22c597bf64413ee4329c8869484d8a1f290f217.tar.xz | |
sb/intel/i82371eb: Do not read PM/SMBus I/O ports at runtime
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.
Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/i82371eb/acpi/i82371eb.asl | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 17fd61d604..e3e67eadee 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -30,10 +30,6 @@ Device (PX40) { Name (BUF1, ResourceTemplate () { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) /* PIIX4E ports */ /* Aliased DMA ports */ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) @@ -51,14 +47,6 @@ Device (PX40) IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) Return (BUF1) } } @@ -145,16 +133,4 @@ Device (PX43) }) Return (BUF1) } - - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } } |