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authorMartin Roth <martinroth@chromium.org>2016-07-18 10:56:12 -0600
committerNico Huber <nico.h@gmx.de>2016-07-19 23:39:32 +0200
commite28ac06868225cc60d85246d0d10f4c0e85f25bb (patch)
treeeb8b9afc434ce41d9196acb5738a788b6f73442a
parent00aa45391ddb22b5ac24151d54615ca1d89eb745 (diff)
downloadcoreboot-e28ac06868225cc60d85246d0d10f4c0e85f25bb.tar.xz
rockchip/rk3399: Remove unused variable
The 'speed' variable isn't being used after refactoring. Change-Id: Id27a920c61b2bba18d391a7bfefe570235402dec Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15749 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/rockchip/rk3399/sdram.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 5ef6479399..293a0f2108 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -313,7 +313,6 @@ static void phy_io_config(u32 channel,
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
u32 vref_mode, vref_value;
u32 mode_sel = 0;
- u32 speed;
u32 reg_value;
/* vref setting */
@@ -363,15 +362,6 @@ static void phy_io_config(u32 channel,
/* PHY_939 PHY_PAD_CS_DRIVE */
clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
- if (sdram_params->ddr_freq < 400 * MHz)
- speed = 0x0;
- else if (sdram_params->ddr_freq < 800 * MHz)
- speed = 0x1;
- else if (sdram_params->ddr_freq < 1200 * MHz)
- speed = 0x2;
- else
- die("Halting: Unknown DRAM speed.\n");
-
/* PHY_924 PHY_PAD_FDBK_DRIVE */
clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21);
/* PHY_926 PHY_PAD_DATA_DRIVE */