diff options
author | Matt DeVillier <matt.devillier@puri.sm> | 2021-04-01 14:03:03 -0500 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-18 20:39:23 +0000 |
commit | e79431288209f239600874b8f0c45a9490fa0ed6 (patch) | |
tree | 13d9c989198bb829977faefde5aab95c67b24c75 | |
parent | ab3fb6bba3b3b91b2c8e32df727af7aab4fa6884 (diff) | |
download | coreboot-e79431288209f239600874b8f0c45a9490fa0ed6.tar.xz |
mb/purism/librem_14: Update GPIO config
Update GPIO config based on review of latest schematics:
- LAN/WLAN reset lines are NC
- SDIO lines configured via GPP_G0-G7
- DMIC lines are wired directly to codec, not PCH, so GPP_D17-20
are set to NC
- Pads GPP_H0-H3 are configured for I2S2
- Pads GPP_H7-H9 are straps for board revision, so treated as GPI
- CPU_C10_GATE# is NC
- PWRBTN# does not need an internal pull-up
- GPP_C20-23 are configured for M.2 UART
- SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups
- GPP_C6/C7 set to I2C1 for future use
- GPP_E15 changed from SCI to SMI, edge triggered
Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c | 121 |
1 files changed, 61 insertions, 60 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c index e39c8884f1..a12a305275 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c @@ -129,11 +129,11 @@ static const struct pad_config gpio_table[] = { /* GPP_B15 - NC */ PAD_NC(GPP_B15, NONE), - /* GPP_B16 - LAN_RST */ - PAD_CFG_GPO(GPP_B16, 0, PLTRST), + /* GPP_B16 - NC */ + PAD_NC(GPP_B16, NONE), - /* GPP_B17 - WLAN_PCIE_RST */ - PAD_CFG_GPO(GPP_B17, 0, PLTRST), + /* GPP_B17 - NC */ + PAD_NC(GPP_B17, NONE), /* GPP_B18 - NC */ PAD_NC(GPP_B18, NONE), @@ -155,28 +155,29 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_G ------- */ - /* GPP_G0 - NC */ - PAD_NC(GPP_G0, NONE), + /* SDIO on M.2 slot */ + /* GPP_G0 - SD_CMD */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), - /* GPP_G1 - NC */ - PAD_NC(GPP_G1, NONE), + /* GPP_G1 - SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), - /* GPP_G2 - NC */ - PAD_NC(GPP_G2, NONE), + /* GPP_G2 - SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), - /* GPP_G3 - NC */ - PAD_NC(GPP_G3, NONE), + /* GPP_G3 - SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), - /* GPP_G4 - NC */ - PAD_NC(GPP_G4, NONE), + /* GPP_G4 - SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), - /* GPP_G5 - NC */ - PAD_NC(GPP_G5, UP_20K), + /* GPP_G5 - SD_CD#, NC */ + PAD_NC(GPP_G5, DN_20K), - /* GPP_G6 - NC */ - PAD_NC(GPP_G6, NONE), + /* GPP_G6 - SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* GPP_G7 - NC */ + /* GPP_G7 - SD_WP, NC */ PAD_NC(GPP_G7, DN_20K), /* ------- GPIO Group GPP_D ------- */ @@ -232,17 +233,17 @@ static const struct pad_config gpio_table[] = { /* GPP_D16 - NC */ PAD_NC(GPP_D16, NONE), - /* GPP_D17 - DMIC_CLK1 */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D17 - NC */ + PAD_NC(GPP_D17, NONE), - /* GPP_D18 - DMIC_DATA1 */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D18 - NC */ + PAD_NC(GPP_D18, NONE), - /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D19 - NC */ + PAD_NC(GPP_D19, NONE), - /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D20 - NC */ + PAD_NC(GPP_D20, NONE), /* GPP_D21 - NC */ PAD_NC(GPP_D21, NONE), @@ -329,17 +330,17 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_H ------- */ - /* GPP_H0 - M.2_BT_PCMCLK */ - PAD_NC(GPP_H0, UP_20K), + /* GPP_H0 - I2S2_SCLK */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), - /* GPP_H1 - M.2_BT_PCMSYNC */ - PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + /* GPP_H1 - I2S2_SFRM */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), - /* GPP_H2 - M.2_BT_PCMOUT */ - PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + /* GPP_H2 - I2S2_TXD */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), - /* GPP_H3 - M.2_BT_PCMIN */ - PAD_CFG_GPO(GPP_H3, 1, PLTRST), + /* GPP_H3 - I2S2_RXD */ + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* GPP_H4 - NC */ PAD_NC(GPP_H4, NONE), @@ -350,14 +351,14 @@ static const struct pad_config gpio_table[] = { /* GPP_H6 - NC */ PAD_NC(GPP_H6, NONE), - /* GPP_H7 - NC */ - PAD_NC(GPP_H7, NONE), + /* GPP_H7 - MBV_DET1_PCH */ + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), - /* GPP_H8 - NC */ - PAD_NC(GPP_H8, NONE), + /* GPP_H8 - MBV_DET2_PCH */ + PAD_CFG_GPI(GPP_H8, NONE, PLTRST), - /* GPP_H9 - NC */ - PAD_NC(GPP_H9, NONE), + /* GPP_H9 - MBV_DET3_PCH */ + PAD_CFG_GPI(GPP_H9, NONE, PLTRST), /* GPP_H10 - NC */ PAD_NC(GPP_H10, NONE), @@ -383,8 +384,8 @@ static const struct pad_config gpio_table[] = { /* GPP_H17 - NC */ PAD_NC(GPP_H17, NONE), - /* GPP_H18 - CPU_C10_GATE# */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H18 - NC */ + PAD_NC(GPP_H18, NONE), /* GPP_H19 - NC */ PAD_NC(GPP_H19, NONE), @@ -413,7 +414,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), /* GPD3 - PRWBTN# */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), @@ -459,11 +460,11 @@ static const struct pad_config gpio_table[] = { /* GPP_C5 - NC */ PAD_NC(GPP_C5, NONE), - /* GPP_C6 - NC */ - PAD_NC(GPP_C6, NONE), + /* GPP_C6 - SMBL1CLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), - /* GPP_C7 - NC */ - PAD_NC(GPP_C7, NONE), + /* GPP_C7 - SMBL1DATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* GPP_C8 - NC */ PAD_NC(GPP_C8, NONE), @@ -501,17 +502,17 @@ static const struct pad_config gpio_table[] = { /* GPP_C19 - NC */ PAD_NC(GPP_C19, NONE), - /* GPP_C20 - NC */ - PAD_NC(GPP_C20, NONE), + /* GPP_C20 - M.2 UART RXD */ + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), - /* GPP_C21 - NC */ - PAD_NC(GPP_C21, NONE), + /* GPP_C21 - M.2 UART TXD */ + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), - /* GPP_C22 - NC */ - PAD_NC(GPP_C22, NONE), + /* GPP_C22 - M.2 UART RTS# */ + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), - /* GPP_C23 - NC */ - PAD_NC(GPP_C23, NONE), + /* GPP_C23 - M.2 UART CTS# */ + PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), /* ------- GPIO Group GPP_E ------- */ @@ -519,10 +520,10 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E0, NONE), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), /* GPP_E3 - NC */ PAD_NC(GPP_E3, NONE), @@ -561,10 +562,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* GPP_E15 - SMC_EXTSMI# */ - PAD_CFG_GPI_SCI_LOW(GPP_E15, UP_20K, PLTRST, LEVEL), + PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), /* GPP_E16 - SMC_RUNTIME_SCI# */ - PAD_CFG_GPI_SCI_LOW(GPP_E16, UP_20K, PLTRST, LEVEL), + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), /* GPP_E17 - EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), |