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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-12 21:08:27 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 08:21:33 +0000 |
| commit | ec38570ead077f6fe37c017c857915ea6cca3951 (patch) | |
| tree | bbc7542a8d9beaee5196d9e93b177c9a89ac7b75 | |
| parent | fc36e9fb0e81cf7b6b17a51f023d030b0ab117f9 (diff) | |
| download | coreboot-ec38570ead077f6fe37c017c857915ea6cca3951.tar.xz | |
nb/intel/sandybridge: Correct description of QCLK
QCLK means "quadrature clock", and is equivalent to one half of a full
clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid.
Change-Id: I7089fc32381addc280a71761a377075f107b5c62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index c43378d7f1..b93902aa38 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -433,7 +433,8 @@ typedef struct ramctr_timing_st { #define MIN_CAS 4 /* - * 1 QCLK (quarter of a clock cycle) equals 64 PI (phase interpolator) ticks. + * 1 QCLK (quadrature clock) is one half of a full clock cycle (tCK). + * In addition, 64 PI (phase interpolator) ticks are equal to 1 QCLK. * Logic delay values in I/O register bitfields are expressed in QCLKs. */ #define QCLK_PI 64 |