diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-28 14:20:36 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:08:06 +0000 |
| commit | ec99cd911215b04f71d511a46ea136f168c48b1a (patch) | |
| tree | 4a330a74cbe93da336609fbae282ffb2d9599f15 | |
| parent | ee7fb34dcb495460b4a172ed10b3aebcacdaacad (diff) | |
| download | coreboot-ec99cd911215b04f71d511a46ea136f168c48b1a.tar.xz | |
sb/intel/bd82x6x: Clean up early_thermal.c
Use proper types in readXp functions, define `PCH_THERMAL_DEV`, clean up
comments a bit, and use `RCBA32_AND_OR` instead of read32/write32.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I95e054d6e52706e06e313068e61484f6cb9a64e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50038
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_thermal.c | 29 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
2 files changed, 14 insertions, 16 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 46874b2dc4..d0051355da 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -6,38 +6,35 @@ #include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> -static void write8p(uintptr_t addr, uint32_t val) +static void write8p(uintptr_t addr, uint8_t val) { - write8((u8 *)addr, val); + write8((uint8_t *)addr, val); } -static void write16p(uintptr_t addr, uint32_t val) +static void write16p(uintptr_t addr, uint16_t val) { - write16((u16 *)addr, val); + write16((uint16_t *)addr, val); } static uint16_t read16p(uintptr_t addr) { - return read16((u16 *)addr); + return read16((uint16_t *)addr); } /* Temporary address for the thermal BAR */ #define TBARB_TEMP 0x40000000 /* Early thermal init, must be done prior to giving ME its memory - which is done at the end of raminit. */ + which is done at the end of raminit */ void early_thermal_init(void) { - pci_devfn_t dev; - msr_t msr; + const pci_devfn_t dev = PCH_THERMAL_DEV; - dev = PCI_DEV(0x0, 0x1f, 0x6); - - /* Program address for temporary BAR. */ + /* Program address for temporary BAR */ pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0); - /* Activate temporary BAR. */ + /* Activate temporary BAR */ pci_or_config32(dev, 0x40, 5); write16p(TBARB_TEMP + 0x04, 0x3a2b); @@ -48,9 +45,9 @@ void early_thermal_init(void) write8p(TBARB_TEMP + 0x82, 0x00); write8p(TBARB_TEMP + 0x01, 0xba); - /* Perform init. */ - /* Configure TJmax. */ - msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Perform init */ + /* Configure TJmax */ + const msr_t msr = rdmsr(MSR_TEMPERATURE_TARGET); write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ write16p(TBARB_TEMP + 0x16, 0x808c); @@ -65,5 +62,5 @@ void early_thermal_init(void) pci_write_config32(dev, 0x40, 0); - write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + RCBA32_AND_OR(0x38b0, 0xffff8003, 0x403c); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1840a2b0d2..fa0f712173 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -85,6 +85,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) +#define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6) #define PCH_PCIE_DEV_SLOT 28 #define PCH_IOAPIC_PCI_BUS 250 #define PCH_IOAPIC_PCI_SLOT 31 |