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| author | Furquan Shaikh <furquan@google.com> | 2020-05-15 18:50:09 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-17 04:06:03 +0000 |
| commit | edf2c8eb557c8ee16e72a2177985463e66e194c9 (patch) | |
| tree | b2bd9e27e535232d91b87548702ef225bdad6538 | |
| parent | 6186cbcdc7c51362d139548da0acb5dc2af6a7e4 (diff) | |
| download | coreboot-edf2c8eb557c8ee16e72a2177985463e66e194c9.tar.xz | |
soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax
This change updates northbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 33900273fb..1f58dfe720 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -183,21 +183,21 @@ Method (_CRS, 0, Serialized) * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (\_SB.PCI0.MCHC.TLUD, PMIN) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \_SB.PCI0.MCHC.TLUD + PLEN = PMAX - PMIN + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) - Store (0, MSEN) + MSEN = 0 } Else { CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._LEN, MLEN) /* Set 64bit MMIO resource base and length */ - Store (A4GS, MLEN) - Store (A4GB, MMIN) - Subtract (Add (MMIN, MLEN), 1, MMAX) + MLEN = A4GS + MMIN = A4GB + MMAX = MMIN + MLEN - 1 } Return (MCRS) @@ -206,35 +206,35 @@ Method (_CRS, 0, Serialized) /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Local0 = \_SB.PCI0.MCHC.MHBR << 15 Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.EPBR << 12 Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Local0 = \_SB.PCI0.MCHC.PXBR << 26 Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Local0 = \_SB.PCI0.MCHC.DIBR << 12 Return (Local0) } @@ -282,22 +282,22 @@ Device (PDRC) }) CreateDwordField (BUF0, MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB (), MBR0) + MBR0 = \_SB.PCI0.GMHB () CreateDwordField (BUF0, DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB (), DBR0) + DBR0 = \_SB.PCI0.GDMB () CreateDwordField (BUF0, EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB (), EBR0) + EBR0 = \_SB.PCI0.GEPB () CreateDwordField (BUF0, PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB (), XBR0) + XBR0 = \_SB.PCI0.GPCB () CreateDwordField (BUF0, PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL (), XSZ0) + XSZ0 = \_SB.PCI0.GPCL () CreateDwordField (BUF0, FIOH._BAS, FBR0) - Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + FBR0 = 0x100000000 - CONFIG_ROM_SIZE Return (BUF0) } |