soc/amd/common: Refactor and consolidate code for spi base

Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.

This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.

BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 40 insertions, 41 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index d226e0c05d..fa52da7535 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -3,6 +3,8 @@
 #ifndef __AMDBLOCKS_SPI_H__
 #define __AMDBLOCKS_SPI_H__
 
+#include <stdint.h>
+
 #define SPI_CNTRL0			0x00
 #define   SPI_BUSY			BIT(31)
 
@@ -94,4 +96,10 @@ void fch_spi_early_init(void);
  */
 void fch_spi_config_modes(void);
 
+/* Set the SPI base address variable */
+void spi_set_base(void *base);
+
+/* Get the SPI base address variable's value */
+uintptr_t spi_get_bar(void);
+
 #endif /* __AMDBLOCKS_SPI_H__ */
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index bf64c3f260..bac1452709 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -4,28 +4,30 @@
 #include <amdblocks/lpc.h>
 #include <amdblocks/spi.h>
 #include <arch/mmio.h>
+#include <assert.h>
 #include <console/console.h>
 #include <soc/iomap.h>
 #include <stdint.h>
 
-static uintptr_t fch_spi_base(void)
-{
-	uintptr_t base;
-
-	base = lpc_get_spibase();
+static uintptr_t spi_base;
 
-	if (base)
-		return base;
+void spi_set_base(void *base)
+{
+	spi_base = (uintptr_t)base;
+}
 
-	lpc_set_spibase(SPI_BASE_ADDRESS);
-	lpc_enable_spi_rom(SPI_ROM_ENABLE);
+uintptr_t spi_get_bar(void)
+{
+	if (ENV_X86 && !spi_base)
+		spi_set_base((void *)lpc_get_spibase());
+	ASSERT(spi_base);
 
-	return SPI_BASE_ADDRESS;
+	return spi_base;
 }
 
 static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
 {
-	uintptr_t base = fch_spi_base();
+	uintptr_t base = spi_get_bar();
 
 	write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
 	write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
@@ -33,7 +35,7 @@ static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
 
 static void fch_spi_disable_4dw_burst(void)
 {
-	uintptr_t base = fch_spi_base();
+	uintptr_t base = spi_get_bar();
 	uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG));
 
 	write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST);
@@ -41,7 +43,7 @@ static void fch_spi_disable_4dw_burst(void)
 
 static void fch_spi_set_read_mode(u32 mode)
 {
-	uintptr_t base = fch_spi_base();
+	uintptr_t base = spi_get_bar();
 	uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK;
 
 	write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
@@ -77,7 +79,6 @@ void fch_spi_config_modes(void)
 
 void fch_spi_early_init(void)
 {
-	lpc_set_spibase(SPI_BASE_ADDRESS);
 	lpc_enable_spi_rom(SPI_ROM_ENABLE);
 	lpc_enable_spi_prefetch();
 	fch_spi_disable_4dw_burst();
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index 13ad0cd32d..0be6b0e72f 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -30,26 +30,24 @@
 #define   SPI_FIFO_RD_PTR_SHIFT		16
 #define   SPI_FIFO_RD_PTR_MASK		0x7f
 
-static uint32_t spibar;
-
-static inline uint8_t spi_read8(uint8_t reg)
+static uint8_t spi_read8(uint8_t reg)
 {
-	return read8((void *)(spibar + reg));
+	return read8((void *)(spi_get_bar() + reg));
 }
 
-static inline uint32_t spi_read32(uint8_t reg)
+static uint32_t spi_read32(uint8_t reg)
 {
-	return read32((void *)(spibar + reg));
+	return read32((void *)(spi_get_bar() + reg));
 }
 
-static inline void spi_write8(uint8_t reg, uint8_t val)
+static void spi_write8(uint8_t reg, uint8_t val)
 {
-	write8((void *)(spibar + reg), val);
+	write8((void *)(spi_get_bar() + reg), val);
 }
 
-static inline void spi_write32(uint8_t reg, uint32_t val)
+static void spi_write32(uint8_t reg, uint32_t val)
 {
-	write32((void *)(spibar + reg), val);
+	write32((void *)(spi_get_bar() + reg), val);
 }
 
 static void dump_state(const char *str, u8 phase)
@@ -64,7 +62,7 @@ static void dump_state(const char *str, u8 phase)
 	printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0));
 	printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS));
 
-	addr = spibar + SPI_FIFO;
+	addr = spi_get_bar() + SPI_FIFO;
 	if (phase == 0) {
 		dump_size = spi_read8(SPI_TX_BYTE_COUNT);
 		printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size);
@@ -111,8 +109,7 @@ static int execute_command(void)
 
 void spi_init(void)
 {
-	spibar = lpc_get_spibase();
-	printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, spibar);
+	printk(BIOS_DEBUG, "%s: SPI BAR at 0x%08lx\n", __func__, spi_get_bar());
 }
 
 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 15219b42a2..534f33d46c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/spi.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <bootstate.h>
@@ -256,25 +257,17 @@ void sb_clk_output_48Mhz(u32 osc)
 	misc_write32(MISC_CLK_CNTL1, ctrl);
 }
 
-static uintptr_t sb_init_spi_base(void)
+static void sb_init_spi_base(void)
 {
-	uintptr_t base;
-
 	/* Make sure the base address is predictable */
-	base = lpc_get_spibase();
-
-	if (base)
-		return base;
-
-	lpc_set_spibase(SPI_BASE_ADDRESS);
+	if (ENV_X86)
+		lpc_set_spibase(SPI_BASE_ADDRESS);
 	lpc_enable_spi_rom(SPI_ROM_ENABLE);
-
-	return SPI_BASE_ADDRESS;
 }
 
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
 {
-	uintptr_t base = sb_init_spi_base();
+	uintptr_t base = spi_get_bar();
 	write16((void *)(base + SPI100_SPEED_CONFIG),
 				(norm << SPI_NORM_SPEED_NEW_SH) |
 				(fast << SPI_FAST_SPEED_NEW_SH) |
@@ -285,7 +278,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
 
 void sb_disable_4dw_burst(void)
 {
-	uintptr_t base = sb_init_spi_base();
+	uintptr_t base = spi_get_bar();
 	write16((void *)(base + SPI100_HOST_PREF_CONFIG),
 			read16((void *)(base + SPI100_HOST_PREF_CONFIG))
 					& ~SPI_RD4DW_EN_HOST);
@@ -293,7 +286,7 @@ void sb_disable_4dw_burst(void)
 
 void sb_read_mode(u32 mode)
 {
-	uintptr_t base = sb_init_spi_base();
+	uintptr_t base = spi_get_bar();
 	write32((void *)(base + SPI_CNTRL0),
 			(read32((void *)(base + SPI_CNTRL0))
 					& ~SPI_READ_MODE_MASK) | mode);