diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-06-11 11:29:21 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-12 04:31:59 +0000 |
| commit | f2ccd072ccb0ff3e256b233a25a26f71c20b78ed (patch) | |
| tree | 86719f6f23f690bd799af4973e6918b9b814512b | |
| parent | d5f1e0f9734273f79ebd313bb6a17eda04c22c11 (diff) | |
| download | coreboot-f2ccd072ccb0ff3e256b233a25a26f71c20b78ed.tar.xz | |
mb/google/hatch: Remove unused USB2 port from Noibat
This port isn't packed on the board, so remove from
the devicetree.
BUG=b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/hatch/variants/noibat/overridetree.cb | 23 |
1 files changed, 2 insertions, 21 deletions
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index ea6e177024..050a75a4cc 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -49,14 +49,7 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "{ .enable = 1, .ocpin = OC0, @@ -82,7 +75,7 @@ chip soc/intel/cannonlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4 # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -223,12 +216,6 @@ chip soc/intel/cannonlake device usb 2.3 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi register "desc" = ""USB2 Type-A Rear Left"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 0)" @@ -267,12 +254,6 @@ chip soc/intel/cannonlake register "group" = "ACPI_PLD_GROUP(1, 0)" device usb 3.4 on end end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end end end end # USB xHCI |