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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-01-08 17:28:35 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-01-08 17:28:35 +0000
commitf2ecb74023b912c62de760cb440a9f7ef4ddb3ff (patch)
tree3f5b49ca2c68863155dbf595bcd8bca0e7b0b621
parent4d1aa0a9ebdde08f80406b3ea4e14b9bd8a5e9d4 (diff)
downloadcoreboot-f2ecb74023b912c62de760cb440a9f7ef4ddb3ff.tar.xz
Remove some DOS line endings accidentially introduced in r3014.
No code lines affected, so svn blame will not be messed up. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 748223a06b..1a00c1e1ff 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -1,6 +1,6 @@
/*
* This file is part of the LinuxBIOS project.
- *
+ *
* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -15,11 +15,11 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
+ */
+
#define CacheSize DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
-
+
/* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
@@ -36,7 +36,7 @@
/*for normal part %ebx already contain cpu_init_detected from fallback call */
cache_as_ram_setup:
-
+
movb $0xA0, %al
outb %al, $0x80
@@ -107,7 +107,7 @@ enable_fixed_mtrr_dram_modify:
/* Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
-
+
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
@@ -245,7 +245,7 @@ clear_fixed_var_mtrr_out:
movb $0xA1, %al
outb %al, $0x80
-
+
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff, %eax
@@ -259,7 +259,7 @@ clear_fixed_var_mtrr_out:
bt $8, %eax /*BSC */
jnc CAR_FAM10_ap
#endif
-
+
movb $0xA2, %al
outb %al, $0x80
@@ -280,7 +280,7 @@ clear_fixed_var_mtrr_out:
/* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp
-
+
movb $0xA3, %al
outb %al, $0x80
@@ -316,7 +316,7 @@ CAR_FAM10_ap:
jc roll_cfg
rolb %cl, %bl
roll_cfg:
-
+
/* calculate stack pointer */
movl $CacheSizeAPStack, %eax
mull %ebx
@@ -337,7 +337,7 @@ CAR_FAM10_ap_out:
/* Restore the BIST result */
movl %ebp, %eax
-
+
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %ebx /* init detected */