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| author | Aaron Durbin <adurbin@chromium.org> | 2017-04-27 14:14:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-04-28 15:58:49 +0200 |
| commit | f39692ee3e6cd63714e9ec1b3a3243636bb5ca1b (patch) | |
| tree | 09c7e04b7eb27c33fcfb3f811398dc9336a4704e | |
| parent | 9c86aafe5a18068edb824faf4d2e44f0fefc6411 (diff) | |
| download | coreboot-f39692ee3e6cd63714e9ec1b3a3243636bb5ca1b.tar.xz | |
soc/intel/apollolake: fix system reset eventlog
The SRS bit which is supposed to indicate reset button press
is non-functional. If it did work the system reset event it
was associated with is overly specific. Therefore, use the
warm reset status bit.
BUG=b:37687843
Change-Id: I34dd09c03d2bca72da9a5cdf23121e0d0e621fa6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19484
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/apollolake/elog.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index f061188755..1e9b7d8329 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -73,7 +73,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_RTC_RESET); /* System Reset */ - if (ps->gen_pmcon1 & SRS) + if (ps->gen_pmcon1 & WARM_RESET_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* TCO Timeout */ |