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| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 14:12:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:28:05 +0000 |
| commit | f4fa1e1d06b5c68b746274c39f23cc8b05801d90 (patch) | |
| tree | 71791abd70eaa3d21b38c284ded82eee8bdf4743 | |
| parent | 90de10c17a2d72065592875b4af206e9cb1a7feb (diff) | |
| download | coreboot-f4fa1e1d06b5c68b746274c39f23cc8b05801d90.tar.xz | |
nb/intel/haswell: Deduplicate PCIEXBAR decoding
Add `decode_pcie_bar` for consistency with other Intel northbridges.
Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/haswell/acpi.c | 39 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 5 |
3 files changed, 11 insertions, 35 deletions
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc4d1..cc4487c43c 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -2,6 +2,7 @@ #include <types.h> #include <console/console.h> +#include <commonlib/helpers.h> #include <acpi/acpi.h> #include <device/device.h> #include <device/pci_ops.h> @@ -10,44 +11,12 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - u32 mask; - - dev = pcidev_on_root(0, 0); - if (!dev) - return current; - - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; + u32 length, pciexbar; - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - pciexbar = pciexbar_reg & mask; - max_buses = 256; - break; - case 1: /* 128M */ - mask |= (1 << 27); - pciexbar = pciexbar_reg & mask; - max_buses = 128; - break; - case 2: /* 64M */ - mask |= (1 << 27) | (1 << 26); - pciexbar = pciexbar_reg & mask; - max_buses = 64; - break; - default: /* RSVD */ + if (!decode_pcie_bar(&pciexbar, &length)) return current; - } - if (!pciexbar) - return current; + const int max_buses = length / MiB; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, max_buses - 1); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 5e28336b0c..9a99c2abc5 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -157,6 +157,8 @@ void haswell_unhide_peg(void); void report_platform_info(void); +int decode_pcie_bar(u32 *const base, u32 *const len); + #include <device/device.h> struct acpi_rsdp; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0a5af4fa7b..e1c26d162c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -51,6 +51,11 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * return 0; } +int decode_pcie_bar(u32 *const base, u32 *const len) +{ + return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len); +} + static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) |