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authorBarnali Sarkar <barnali.sarkar@intel.com>2018-01-11 16:40:54 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-01-25 05:48:01 +0000
commitf7f01f70a4129b2854ae33ff7461e356df424767 (patch)
treed947e8d70c5ed923fcdd50c988dd4f861df5d320
parenta2fc1aee446f7cafa0e275c69fcb54adb5bf233d (diff)
downloadcoreboot-f7f01f70a4129b2854ae33ff7461e356df424767.tar.xz
soc/intel/skylake: Send correct ddr_type to SMBIOS Table
The FSP 2.0 Memory_Info_HOB for KBL is not sending "MemoryType" value as what is required for SMBIOS Table according to SMBIOS Spec. Thus, converting the value retrieved from FSP HOB to the correct value. This change will not be required for upcoming SOCs since FSP have fixed this issue in its next platforms and thus it will take care and send the correct value in "MemoryType" field based on SMBIOS spec. Thus this conversion from coreboot will not be required in the next platfoms. "MemoryType" value can be directly passed to dimm_info_fill() function. BUG=none BRANCH=none TEST=Tested in Soraka, and getting the value as 0x1D for LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17 will also show correct information. Currently, it was showing "Unknown". Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index d6ec41f257..d4606a477a 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -28,6 +28,7 @@
#include <fsp/memmap.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
+#include <smbios.h>
#include <soc/intel/common/smbios.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -48,6 +49,7 @@ static void save_dimm_info(void)
{
int channel, dimm, dimm_max, index;
size_t hob_size;
+ uint8_t ddr_type;
const CONTROLLER_INFO *ctrlr_info;
const CHANNEL_INFO *channel_info;
const DIMM_INFO *src_dimm;
@@ -91,10 +93,25 @@ static void save_dimm_info(void)
if (src_dimm->Status != DIMM_PRESENT)
continue;
+ switch(memory_info_hob->MemoryType) {
+ case MRC_DDR_TYPE_DDR4:
+ ddr_type = MEMORY_DEVICE_DDR4;
+ break;
+ case MRC_DDR_TYPE_DDR3:
+ ddr_type = MEMORY_DEVICE_DDR3;
+ break;
+ case MRC_DDR_TYPE_LPDDR3:
+ ddr_type = MEMORY_DEVICE_LPDDR3;
+ break;
+ default:
+ ddr_type = MEMORY_DEVICE_UNKNOWN;
+ break;
+ }
+
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
- memory_info_hob->MemoryType,
+ ddr_type,
memory_info_hob->ConfiguredMemoryClockSpeed,
channel_info->ChannelId,
src_dimm->DimmId,